Kayhan Kucukcakar
Kayhan Kucukcakar
Verified email at ansys.com
Title
Cited by
Cited by
Year
Method for designing a product having hardware and software components and product therefor
K Kuçukçakar
US Patent 5,815,715, 1998
821998
CHOP: A constraint-driven system-level partitioner
K Kücukçakar, AC Parker
Proceedings of the 28th ACM/IEEE Design Automation Conference, 514-519, 1991
791991
Experience with the ADAM synthesis system
R Jain, K Kucukcakar, MJ Mlinar, AC Parker
Design Automation, 1989. 26th Conference on, 56-61, 1989
761989
Exploiting setup–hold-time interdependence in static timing analysis.
EGF Emre Salman, Ali Dasdan, Feroze Taraporevala
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
652007
Data Path tradeoffs using MABAL
K Küçükçakar, AC Parker
Proceedings of the 27th ACM/IEEE Design Automation Conference, 511-516, 1990
641990
An ASIP design methodology for embedded systems
K Kucukcakar
Hardware/Software Codesign, 1999.(CODES'99) Proceedings of the Seventh …, 1999
631999
Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units
K Kucukcakar, CT Chen
US Patent 6,138,229, 2000
482000
Method and apparatus for determining the performance of an integrated circuit
K Kucukcakar, A Dasdan, H Damerdji
US Patent 7,650,580, 2010
362010
Pessimism reduction in static timing analysis using interdependent setup and hold times
E Salman, EG Friedman, A Dasdan, F Taraporevala, K Kucukcakar
Proceedings of the 7th International Symposium on Quality Electronic Design …, 2006
322006
Method and apparatus for characterizing static and dynamic operation of an architectural system
K Kucukcakar, CT Chen, J Gong, TE Tkacik
US Patent 5,907,698, 1999
321999
Simultaneous Multi-Corner Static Timing Analysis Using Samples-Based Static Timing Infrastructure
P Ghanta, A Goel, FP Taraporevala, M Ovchinnikov, J Liu, K Kucukcakar, ...
US Patent 8,615,727, 2010
262010
System and method for providing distributed static timing analysis with merged results
K Küçükçakar, S Hollands, B Clerkin, L Mize, Q Wu, S Sripada, AJ Seigel
US Patent 7,739,098, 2010
232010
Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis
A Dasdan, E Salman, FP Taraporevala, K Kucukcakar
US Patent 7,506,293, 2009
232009
Method and apparatus for reducing timing pessimism during static timing analysis
K Küçükçakar, A Dasdan
US Patent 7,237,212, 2007
222007
Matisse: an architectural design tool for commodity ICs
K Kucukcakar, CT Chen, J Gong, W Philipsen, TE Tkacik
Design & Test of Computers, IEEE 15 (2), 22-33, 1998
221998
Engineering change order process optimization
K Kucukcakar, JC Lin, J Lou
US Patent 7,552,409, 2009
202009
System and method for optimizing exceptions
K Kucukcakar, RN Helaihel
US Patent 6,964,027, 2005
192005
MABAL: A software package for module and bus allocation
K Kucukcakar, AC Parker
International Journal of Computer-Aided VLSI Design, 1989
17*1989
RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS
F DARTU, P FORTNER, K KUCUKCAKAR, Q WU, INC SYNOPSYS
US Patent 8,443,328, 2013
162013
Method for designing an architectural system
K Kucukcakar, CT Chen, WJ Philipsen, TE Tkacik
US Patent 5,912,819, 1999
161999
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