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Dr. Aneela Pathan
Dr. Aneela Pathan
The University Of Larkano
Verified email at quest.edu.pk
Title
Cited by
Cited by
Year
FPGA Based performance analysis of multiplier policies for FIR filter
A Pathan, TD Memon, S Keerio, IH Kalwar
2016 International Conference on Advances in Electrical, Electronic and …, 2016
162016
An approach to LUT based multiplier for short word length DSP systems
TD Memon, A Pathan
2018 International Conference on Signals and Systems (ICSigSys), 276-280, 2018
112018
Sigma-delta modulation based single-bit adaptive DSP algorithms for efficient mobile communication
A Pathan, TD Memon
Circuits, Systems, and Signal Processing 40 (4), 1788-1801, 2021
102021
An optimised 3× 3 shift and add multiplier on FPGA
A Pathan, TD Memon
2017 14th International Bhurban Conference on Applied Sciences and …, 2017
82017
Sigma-delta modulation based adaptive channel equalizer based on Wiener–Hopf Equations
A Pathan, TD Memon
Wireless Personal Communications 116 (2), 1123-1135, 2021
72021
FPGA based implementation and area performance analysis of sigma-delta modulated steepest algorithm for channel equalization
TD Memon, A Pathan, P Beckett
2018 12th International conference on signal processing and communication …, 2018
52018
Analysis of booth multiplier based conventional and short word length FIR filter
A Pathan, R Balal, TD Memon, SA Memon
Mehran University Research Journal of Engineering & Technology 37 (3), 595-602, 2018
52018
A carry-look ahead adder based floating-point multiplier for adaptive filter applications
A Pathan, TD Memon, S Memon
International Journal of Computing and Digital Systems 7 (02), 95-102, 2018
52018
Analysis of existing and proposed 3-bit and multi-bit multiplier algorithms for FIR filters and adaptive channel equalizers on FPGA
A Pathan, TD Memon, FK Sohu, MA Rajput
Quaid-E-Awam University Research Journal of Engineering, Science …, 2021
42021
A correlation-less approach towards adaptive channel equalizer based on Wiener–Hopf equation
A Pathan, TD Memon
Wireless Personal Communications 118 (4), 3539-3548, 2021
42021
Analyzing the impact of sigma-delta modulation on performance parameters of adaptive filters
A Pathan, TD Memon
Wireless Personal Communications 115 (2), 1035-1045, 2020
42020
A Correlation-Less Approach Toward the Steepest-Descent-Based Adaptive Channel Equalizer
A Pathan, TD Memon, RA Mangi
Circuits, Systems, and Signal Processing, 1-13, 2023
22023
An autocorrelation-less single-bit Weiner filter on FPGA
A Pathan, TD Memon, S Raza, R Aziz
Biomedical Signal Processing and Control 86, 105166, 2023
22023
Computationally efficient low-power sigma delta modulation-based image processing algorithm
A Pathan, TD Memon, S Raza, RA Mangi
Mehran University Research Journal Of Engineering & Technology 42 (3), 102-109, 2023
22023
An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA
A Pathan, AH Chandio, R Aziz
2022 International Conference on Emerging Technologies in Electronics …, 2022
12022
FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems.
A Pathan, T Memon
Iranian Journal of Electrical & Electronic Engineering 17 (4), 2021
12021
FPGA based area-power-performance analysis of LMS filter using conventional and proposed multipliers
A Pathan, TD Memon, FK Sohu
Journal of Physics: Conference Series 1860 (1), 012010, 2021
12021
A novel approach toward optimized image processing using sigma delta modulation
A Pathan, TD Memon, R Aziz, SH Shah
Mehran University Research Journal Of Engineering & Technology 43 (2), 195-204, 2024
2024
A Novel Approach Towards Biometric Recognition System Using Voice and Signature
S Ahmed, A Pathan, FK Sohu, RA Mangi, T Abbasi
Quaid-E-Awam University Research Journal of Engineering, Science …, 2023
2023
A Novel Approach Toward Algorithm Architecture Co-Optimization for the Application of Adaptive Noise Cancellation for Wireless Communication
A Pathan
Sukkur IBA Journal of Computing and Mathematical Sciences 7 (1), 51-59, 2023
2023
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Articles 1–20