Mallika Rathore
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A novel static D-flip-flop topology for low swing clocking
M Rathore, W Liu, E Salman, C Sitik, B Taskin
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 301-306, 2015
Towards TFET based Approximate Computing for Deep Learning
M Rathore, P Milder, E Salman
Stony Brook University Stony Brook United States, 2019
Error Probability Models to Facilitate Approximate Computing in TFET based Circuits
M Rathore, E Salman
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units
M Rathore, P Milder, E Salman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks
M Rathore
The Graduate School, Stony Brook University: Stony Brook, NY., 2015
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