Vivek De
Vivek De
Intel Fellow, Intel Corporation
Verified email at intel.com
Title
Cited by
Cited by
Year
Parameter variations and impact on circuits and microarchitecture
S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi, V De
Proceedings of the 40th annual Design Automation Conference, 338-342, 2003
17392003
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
JW Tschanz, JT Kao, SG Narendra, R Nair, DA Antoniadis, ...
IEEE Journal of Solid-State Circuits 37 (11), 1396-1402, 2002
9062002
A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS
J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010
7612010
A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation
JA Davis, VK De, JD Meindl
IEEE Transactions on Electron Devices 45 (3), 580-589, 1998
486*1998
A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling
J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ...
IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2010
4592010
Technology and design challenges for low power and high performance
V De, S Borkar
Proceedings of the 1999 international symposium on Low power electronics and …, 1999
4371999
Scaling of stack effect and its application for leakage reduction
S Narendra, V De, D Antoniadis, A Chandrakasan, S Borkar
Proceedings of the 2001 international symposium on Low power electronics and …, 2001
4112001
A new technique for standby leakage reduction in high-performance circuits
Y Ye, S Borkar, V De
1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 1998
3931998
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package
P Hazucha, G Schrom, J Hahn, BA Bloechel, P Hack, GE Dermer, ...
IEEE Journal of Solid-State Circuits 40 (4), 838-845, 2005
3752005
Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance
KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ...
IEEE Journal of Solid-State Circuits 44 (1), 49-63, 2008
3742008
Dynamic sleep transistor and body bias for active leakage power control of microprocessors
JW Tschanz, SG Narendra, Y Ye, BA Bloechel, S Borkar, V De
IEEE Journal of Solid-State Circuits 38 (11), 1838-1845, 2003
3662003
Design and optimization of dual-threshold circuits for low-voltage low-power applications
L Wei, Z Chen, K Roy, MC Johnson, Y Ye, VK De
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (1), 16-24, 1999
3651999
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors
J Tschanz, S Narendra, Z Chen, S Borkar, M Sachdev, V De
Proceedings of the 2001 international symposium on Low power electronics and …, 2001
3142001
Intrinsic MOSFET parameter fluctuations due to random dopant placement
X Tang, VK De, JD Meindl
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5 (4), 369-376, 1997
3021997
A 280mV-to-1.2 V wide-operating-range IA-32 processor in 32nm CMOS
S Jain, S Khare, S Yada, V Ambili, P Salihundam, S Ramani, ...
2012 IEEE International Solid-State Circuits Conference, 66-68, 2012
2832012
Design and optimization of low voltage high performance dual threshold CMOS circuits
L Wei, Z Chen, M Johnson, K Roy, V De
Proceedings of the 35th annual Design Automation Conference, 489-494, 1998
2831998
A 45 nm resilient microprocessor core for dynamic variation tolerance
KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ...
IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2010
2802010
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
A Keshavarzi, S Ma, S Narendra, B Bloechel, K Mistry, T Ghani, S Borkar, ...
Proceedings of the 2001 international symposium on Low power electronics and …, 2001
2392001
Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging
J Tschanz, NS Kim, S Dighe, J Howard, G Ruhl, S Vangal, S Narendra, ...
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
2352007
Multiple well transistor circuits having forward body bias
VK De, A Keshavarzi, SG Narendra, SY Borkar
US Patent 6,218,895, 2001
2282001
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