Indrani Paul
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Achieving exascale capabilities through heterogeneous computing
MJ Schulte, M Ignatowski, GH Loh, BM Beckmann, WC Brantley, ...
IEEE Micro 35 (4), 26-36, 2015
Design and Analysis of an APU for Exascale Computing
T Vijayaraghavan, Y Eckert, GH Loh, MJ Schulte, M Ignatowski, ...
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
Harmonia: Balancing compute and memory power in high-performance gpus
I Paul, W Huang, M Arora, S Yalamanchili
ACM SIGARCH Computer Architecture News 43 (3S), 54-65, 2015
Cooperative boosting: Needy versus greedy power management
I Paul, S Manne, M Arora, WL Bircher, S Yalamanchili
ACM SIGARCH Computer Architecture News 41 (3), 285-296, 2013
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on cpu-gpu integrated systems
M Arora, S Manne, I Paul, N Jayasena, DM Tullsen
2015 IEEE 21st international symposium on high performance computer …, 2015
Coordinated energy management in heterogeneous processors
I Paul, V Ravi, S Manne, M Arora, S Yalamanchili
Proceedings of the International Conference on High Performance Computing …, 2013
Dynamic gpgpu power management using adaptive model predictive control
A Majumdar, L Piga, I Paul, JL Greathouse, W Huang, DH Albonesi
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
Design and simulation of local area network using cisco packet tracer
NS Tarkaa, PI Iannah, IT Iber
The International Journal of Engineering and Science 6 (10), 63-77, 2017
Performance impact of virtual machine placement in a datacenter
I Paul, S Yalamanchili, LK John
2012 IEEE 31st International Performance Computing and Communications …, 2012
Measuring and modeling on-chip interconnect power on real hardware
V Adhinarayanan, I Paul, JL Greathouse, W Huang, A Pattnaik, W Feng
2016 IEEE International Symposium on Workload Characterization (IISWC), 1-11, 2016
Balancing computation and communication power in power constrained clusters
L Piga, I Paul, W Huang
US Patent 9,983,652, 2018
Ti-states: Processor power management in the temperature inversion region
Y Zu, W Huang, I Paul, VJ Reddi
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
Power manager for multi-threaded data processor
VT Ravi, M Arora, W Brantley, S Manne, I Paul, M Schulte
US Patent App. 14/015,369, 2015
Distributed memory controller
MR Meswani, DA Roberts, Y Eckert, K Dev, J Kalamatianos, I Paul
US Patent App. 14/862,011, 2017
A taxonomy of gpgpu performance scaling
A Majumdar, G Wu, K Dev, JL Greathouse, I Paul, W Huang, ...
2015 IEEE International Symposium on Workload Characterization, 118-119, 2015
Bandwidth-aware multi-frequency performance estimation mechanism
MAS Bari, L Piga, I Paul
US Patent 10,048,741, 2018
A comparison of core power gating strategies implemented in modern hardware
M Arora, S Manne, Y Eckert, I Paul, N Jayasena, D Tullsen
ACM SIGMETRICS Performance Evaluation Review 42 (1), 559-560, 2014
Performance boosting under reliability and power constraints
Y Kim, LK John, I Paul, S Manne, M Schulte
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 334-341, 2013
Power management across heterogeneous processing units
I Paul, VT Ravi, M Arora, S Manne
US Patent 10,025,361, 2018
Interface to expose interrupt times to hardware
I Paul, M Arora
US Patent App. 14/488,864, 2016
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