Carlos Tokunaga
Carlos Tokunaga
Research Scientist, Intel
Verified email at intel.com
Title
Cited by
Cited by
Year
Razor II: In situ error detection and correction for PVT and SER tolerance
D Blaauw, S Kalaiselvan, K Lai, WH Ma, S Pant, C Tokunaga, S Das, ...
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical …, 2008
864*2008
RazorII: In situ error detection and correction for PVT and SER tolerance
S Das, C Tokunaga, S Pant, WH Ma, S Kalaiselvan, K Lai, DM Bull, ...
IEEE Journal of Solid-State Circuits 44 (1), 32-48, 2009
6482009
A 45 nm resilient microprocessor core for dynamic variation tolerance
KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ...
IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2011
2812011
Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging
J Tschanz, NS Kim, S Dighe, J Howard, G Ruhl, S Vangal, S Narendra, ...
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
2352007
True random number generator with a metastability-based quality control
C Tokunaga, D Blaauw, T Mudge
IEEE Journal of Solid-State Circuits 43 (1), 78-85, 2008
1912008
Securing encryption systems with a switched capacitor current equalizer
C Tokunaga, D Blaauw
IEEE Journal of Solid-State Circuits 45 (1), 23-31, 2010
852010
Secure AES engine with a local switched-capacitor current equalizer
C Tokunaga, D Blaauw
2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009
852009
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance
J Tschanz, K Bowman, SL Lu, P Aseron, M Khellah, A Raychowdhury, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 2010
752010
A 22 nm all-digital dynamically adaptive clock distribution for supply voltage droop tolerance
KA Bowman, C Tokunaga, T Karnik, VK De, JW Tschanz
IEEE Journal of Solid-State Circuits 48 (4), 907-916, 2013
652013
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating
M Cho, S Kim, C Tokunaga, C Augustine, J Kulkarni, K Ravichandran, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 152-153, 2016
462016
Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating
M Cho, S Kim, C Tokunaga, C Augustine, J Kulkarni, K Ravichandran, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016
462016
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
M Cho, ST Kim, C Tokunaga, C Augustine, JP Kulkarni, K Ravichandran, ...
IEEE Journal of Solid-State Circuits, 2016
462016
Timing yield enhancement through soft edge flip-flop based design.
M Wieckowski, YM Park, C Tokunaga, DW Kim, Z Foo, D Sylvester, ...
CICC, 543-546, 2008
432008
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator
ST Kim, YC Shih, K Mazumdar, R Jain, JF Ryan, C Tokunaga, ...
IEEE Journal of Solid-State Circuits, 2016
422016
All-digital circuit-level dynamic variation monitor for silicon debug and adaptive clock control
KA Bowman, C Tokunaga, JW Tschanz, A Raychowdhury, MM Khellah, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 2017-2025, 2011
422011
A 2.3 nJ/frame voice activity detector-based audio front-end for context-aware system-on-chip applications in 32-nm CMOS
A Raychowdhury, C Tokunaga, W Beltman, M Deisher, JW Tschanz, V De
IEEE Journal of Solid-State Circuits 48 (8), 1963-1969, 2013
362013
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency
K Bowman, C Tokunaga, J Tschanz, A Raychowdhury, M Khellah, ...
Custom Integrated Circuits Conference (CICC), 2010 IEEE, 1-4, 2010
342010
A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep
C Tokunaga, JF Ryan, C Augustine, JP Kulkarni, YC Shih, ST Kim, R Jain, ...
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, 2014
302014
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation …
JP Kulkarni, C Tokunaga, PA Aseron, T Nguyen, C Augustine, ...
IEEE Journal of Solid-State Circuits, 2016
232016
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation …
JP Kulkarni, C Tokunaga, P Aseron, T Nguyen, C Augustine, J Tschanz, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
232015
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