Zoran Jakšić
Zoran Jakšić
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Considerations in using OpenCL on GPUs and FPGAs for throughput-oriented genomics workloads
N Cadenelli, Z Jaksić, J Polo, D Carrera
Future Generation Computer Systems 94, 148-159, 2019
Enhancing 6T SRAM cell stability by back gate biasing techniques for10nm SOI FinFETs under process and environmental variations
Z Jaksic, R Canal
Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 Proceedings …, 2012
Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations
Z Jaksic, R Canal
IEEE transactions on electron devices 60 (1), 49-55, 2012
A highly parameterizable framework for conditional restricted Boltzmann machine based workloads accelerated with FPGAs and OpenCL
Z Jakšić, N Cadenelli, DB Prats, J Polo, JLB Garcia, DC Perez
Future Generation Computer Systems 104, 201-211, 2020
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
Z Jakšić, R Canal
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
Z Jaksic, R Canal
Computer Design (ICCD), 2012 IEEE 30th International Conference on, 2012
Effects of FinFET Technology Scaling on 3T and 3T1D Cell Performance Under Process and Enviromental Variations
Z Jakšic, R Canal
Cache memory design in the FinFET era
Z Jakšić
Universitat Politècnica de Catalunya, 2015
Analysis of FinFET technology on memories
E Amat, A Asenov, R Canal, B Cheng, J Cruz, Z Jaksic, M Miranda, ...
On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International, 2012
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