Kanad Basu (কণাদ বসু)
Cited by
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Lossless data compression and real-time decompression
P Mishra, SW Seong, K Basu, W Wang, X Qin, C Murthy
US Patent App. 12/682,808, 2010
Processor description languages
P Mishra, N Dutt
Elsevier, 2011
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator
JJ Zhang, T Gu, K Basu, S Garg
2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018
NIST Post-Quantum CryptographyA Hardware Evaluation Study
K Basu, D Soni, M Nabeel, R Karri, 2019
RATS: Restoration-aware trace signal selection for post-silicon validation
K Basu, P Mishra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (4), 605-613, 2012
Test data compression using efficient bitmask and dictionary selection methods
K Basu, P Mishra
IEEE transactions on very large scale integration (VLSI) systems 18 (9 …, 2009
Fault-tolerant Systolic Array Based Accelerators for Deep Neural Network Execution
J Zhang, K Basu, S Garg
IEEE Design and Test, 2019
Efficient trace signal selection for post silicon validation and debug
K Basu, P Mishra
2011 24th Internatioal Conference on VLSI Design, 352-357, 2011
A Theoretical Study of Hardware Performance Counters-based Malware Detection
K Basu, P Krishnamurthy, F Khorrami, R Karri
IEEE Transactions on Information Forensics and Security, 2020
Hardware-assisted detection of firmware attacks in inverter-based cyberphysical microgrids
AP Kuruvila, I Zografopoulos, K Basu, C Konstantinou
International Journal of Electrical Power & Energy Systems 132, 107150, 2021
Toward functional safety of systolic array-based deep learning hardware accelerators
S Kundu, S Banerjee, A Raha, S Natarajan, K Basu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (3), 485-498, 2021
CAD-Base: An Attack Vector into the Electronics Supply Chain.
K Basu, S Saeed, C Pilato, M Ashraf, M Nabeel, ...
ACM Transactions on Design Automation of Embedded Systems, 2019
Special session: The recent advance in hardware implementation of post-quantum cryptography
J Xie, K Basu, K Gaj, U Guin
2020 IEEE 38th VLSI Test Symposium (VTS), 1-10, 2020
Efficient combination of trace and scan signals for post silicon validation and debug
K Basu, P Mishra, P Patra
2011 IEEE International Test Conference, 1-8, 2011
Benchmarking at the frontier of hardware security: Lessons from logic locking
B Tan, R Karri, N Limaye, A Sengupta, O Sinanoglu, MM Rahman, ...
arXiv preprint arXiv:2006.06806, 2020
A Hardware Evaluation Study of NIST Post-Quantum Cryptographic Signature schemes
D Soni, K Basu, M Nabeel, R Karri
Second-PQC-Standardization-Conference, 2019
Analyzing the efficiency of machine learning classifiers in hardware-based malware detectors
AP Kuruvila, S Kundu, K Basu
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 452-457, 2020
Post-Silicon Validation and Debug
P Mishra, F Farahmandi
Springer International Publishing, 2019
Special session: Reliability analysis for AI/ML hardware
S Kundu, K Basu, M Sadi, T Titirsha, S Song, A Das, U Guin
2021 IEEE 39th VLSI Test Symposium (VTS), 1-10, 2021
Efficient trace data compression using statically selected dictionary
K Basu, P Mishra
29th VLSI Test Symposium, 14-19, 2011
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