Kanad Basu (কণাদ বসু)

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Shamik KunduAdvanced Architecture Research, Intel AIVerified email at intel.com
Ramesh Karri కర్రి రమేష్Professor of Electrical and Computer Engineering, New York UniversityVerified email at nyu.edu
Prabhat MishraProfessor, Univ. of Florida, IEEE Fellow, AAAS Fellow, ACM Distinguished MemberVerified email at ufl.edu
Mohammed Nabeel Thari MoopanResearch Engineer, DFX lab, NYUADVerified email at nyu.edu
Abraham Peedikayil KuruvilaThe University of Texas at DallasVerified email at utdallas.edu
Deepraj SoniNew York UniversityVerified email at nyu.edu
Arnab RahaSenior Research Scientist, Advanced Architecture, NPU, Intel AIVerified email at intel.com
xingyu mengUniversity of Texas at DallasVerified email at utdallas.edu
Ayush ArunachalamFunctional Safety Architect, NXP SemiconductorsVerified email at utdallas.edu
Suvadeep BanerjeeSystems Research Scientist, Strategic CAD Labs, Intel LabsVerified email at intel.com
Najwa AarajTechnology Innovation Institute, Princeton UniversityVerified email at tii.ae
Binod KumarIIT JodhpurVerified email at iitj.ac.in
Christian PilatoAssociate Professor, Politecnico di MilanoVerified email at polimi.it
Masahiro FujitaUniversity of TokyoVerified email at ee.t.u-tokyo.ac.jp
Weixun WangUniversity of FloridaVerified email at cise.ufl.edu
Ujjwal GuinGodbold Associate Professor, ECE, Auburn UniversityVerified email at auburn.edu
Chao LuOak Ridge National LaboratoryVerified email at ornl.gov
Krishnendu ChakrabartyFulton Professor of Microelectronics, School of Electrical and Computer and Energy EngineeringVerified email at asu.edu
Siddharth GargInstitute Associate Professor, New York UniversityVerified email at nyu.edu
Jeff J. ZHANGArizona State UniversityVerified email at seas.harvard.edu

Kanad Basu (কণাদ বসু)

University of Texas at Dallas

Verified email at utdallas.edu - Homepage

Hardware Security Post-Silicon Validation VLSI Testing Functional Safety


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Lossless data compression and real-time decompression P Mishra, SW Seong, K Basu, W Wang, X Qin, C Murthy US Patent App. 12/682,808, 2010	206	2010
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator JJ Zhang, T Gu, K Basu, S Garg 2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018	184	2018
Processor description languages P Mishra, N Dutt Elsevier, 2011	173	2011
NIST Post-Quantum CryptographyA Hardware Evaluation Study K Basu, D Soni, M Nabeel, R Karri https://eprint.iacr.org/2019/047.pdf, 2019	153	2019
RATS: Restoration-aware trace signal selection for post-silicon validation K Basu, P Mishra IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (4), 605-613, 2012	98	2012
Fault-tolerant Systolic Array Based Accelerators for Deep Neural Network Execution J Zhang, K Basu, S Garg IEEE Design and Test, 2019	92	2019
Test data compression using efficient bitmask and dictionary selection methods K Basu, P Mishra IEEE transactions on very large scale integration (VLSI) systems 18 (9 …, 2009	82	2009
Efficient trace signal selection for post silicon validation and debug K Basu, P Mishra 2011 24th Internatioal Conference on VLSI Design, 352-357, 2011	79	2011
Toward functional safety of systolic array-based deep learning hardware accelerators S Kundu, S Banerjee, A Raha, S Natarajan, K Basu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (3), 485-498, 2021	74	2021
A Theoretical Study of Hardware Performance Counters-based Malware Detection K Basu, P Krishnamurthy, F Khorrami, R Karri IEEE Transactions on Information Forensics and Security, 2020	70	2020
Hardware-assisted detection of firmware attacks in inverter-based cyberphysical microgrids AP Kuruvila, I Zografopoulos, K Basu, C Konstantinou International Journal of Electrical Power & Energy Systems 132, 107150, 2021	68	2021
CAD-Base: An Attack Vector into the Electronics Supply Chain. K Basu, S Saeed, C Pilato, M Ashraf, M Nabeel, ... ACM Transactions on Design Automation of Embedded Systems, 2019	58	2019
Special session: The recent advance in hardware implementation of post-quantum cryptography J Xie, K Basu, K Gaj, U Guin 2020 IEEE 38th VLSI Test Symposium (VTS), 1-10, 2020	50	2020
Benchmarking at the frontier of hardware security: Lessons from logic locking B Tan, R Karri, N Limaye, A Sengupta, O Sinanoglu, MM Rahman, ... arXiv preprint arXiv:2006.06806, 2020	44	2020
Efficient combination of trace and scan signals for post silicon validation and debug K Basu, P Mishra, P Patra 2011 IEEE International Test Conference, 1-8, 2011	43	2011
A Hardware Evaluation Study of NIST Post-Quantum Cryptographic Signature schemes D Soni, K Basu, M Nabeel, R Karri Second-PQC-Standardization-Conference, 2019	38	2019
Hardware architectures for post-quantum digital signature schemes D Soni, K Basu, M Nabeel, N Aaraj, M Manzano, R Karri Springer, 2021	37	2021
Post-Silicon Validation and Debug P Mishra, F Farahmandi Springer International Publishing, 2019	35	2019
Satisfiability attack-resistant camouflaged two-dimensional heterostructure devices A Wali, S Kundu, AJ Arnold, G Zhao, K Basu, S Das ACS nano 15 (2), 3453-3467, 2021	34	2021
Analyzing the efficiency of machine learning classifiers in hardware-based malware detectors AP Kuruvila, S Kundu, K Basu 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 452-457, 2020	34	2020

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