| OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator J Park, H Yoon, D Ahn, J Choi, JJ Kim Proceedings of Machine Learning and Systems 2, 363-378, 2020 | 40 | 2020 |
| Maximizing system performance by balancing computation loads in LSTM accelerators J Park, J Kung, W Yi, JJ Kim 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 7-12, 2018 | 26 | 2018 |
| NN-LUT: Neural approximation of non-linear operations for efficient transformer inference J Yu, J Park, S Park, M Kim, S Lee, DH Lee, J Choi Proceedings of the 59th ACM/IEEE Design Automation Conference, 577-582, 2022 | 21 | 2022 |
| Peregrine: A flexible hardware accelerator for LSTM with limited synaptic connection patterns J Kung, J Park, S Park, JJ Kim Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 12 | 2019 |
| Balancing computation loads and optimizing input vector loading in LSTM accelerators J Park, W Yi, D Ahn, J Kung, JJ Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 10 | 2019 |
| GeCo: Classification restricted Boltzmann machine hardware for on-chip semisupervised learning and Bayesian inference W Yi, J Park, JJ Kim IEEE Transactions on Neural Networks and Learning Systems 31 (1), 53-65, 2019 | 10 | 2019 |
| METHOD FOR FORMATTING A WEIGHT MATRIX, ACCELERATOR USING THE FORMATTED WEIGHT MATRIX, AND SYSTEM INCLUDING THE ACCELERATOR JJK Junki Park US Patent App. 16/362,398, 2019 | 8* | 2019 |
| Display apparatus and driving method for the same JJ Kim, DB Lee, JK Park, EW Song US Patent 9,813,070, 2017 | 4 | 2017 |
| Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines J Koo, E Song, E Park, D Kim, J Park, S Ryu, S Yoo, JJ Kim 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 137-140, 2016 | 3 | 2016 |
| Geco: Classification restricted Boltzmann machine hardware for on-chip learning W Yi, J Park, JJ Kim Proceedings of the 28th International Symposium on Rapid System Prototyping …, 2017 | 2 | 2017 |
| METHOD AND APPARATUS FOR PROCESSING MATRIX DATA THROUGH RELAXED PRUNING JJK Junki Park, Jaeha Kung US Patent App. 17/137,803, 2020 | 1* | 2020 |
| Semiconductor devices YOU Junggun, P Junki, S Kim, W Kim, S Sung, H Lee US Patent App. 18/369,236, 2024 | | 2024 |
| Integrated circuit device K Hyunwoo, Y Hwang, G Kim, S Kim, P Junki US Patent App. 17/864,716, 2023 | | 2023 |
| METHOD AND APPARATUS FOR NEURAL NETWORK OPERATION JC Junki Park, Joonsang Yu, Donghyun Lee US Patent App. 17/887,183, 2022 | | 2022 |
| Hardware accelerator and hardware accelerator method JJ Junki Park, Junsang Yu CN Patent App. 202210115706.7, 2022 | | 2022 |
| 뉴럴 네트워크 연산 방법 및 장치 JC Junki Park, Joonsang Yu, Donghyun Lee KR Patent App. 1,020,210,138,434, 2021 | | 2021 |
| HARDWARE ACCELERATOR METHOD AND DEVICE JJ Junki Park, Junsang Yu US Patent App. 17/499,149, 2021 | | 2021 |
| 하드웨어 가속기에서의 비선형 함수 계산 방법 및 장치 JJ Junki Park, Joonsang Yu KR Patent App. 1,020,210,065,369, 2020 | | 2020 |
| METHOD OF FORMATTING A WEIGHT MATRIX, AN ACCELERATOR USING THE FORMATTED WEIGHT MATRIX, AND A SYSTEM INCLUDING THE ACCELERATOR EKIM Junki Park, Jae-Joon Kim, Youngjae JIN US Patent App. 16/748,706, 2020 | | 2020 |
| 완화된 프루닝을 통한 행렬 데이터 처리 방법 및 그 장치 JJK Junki Park, Jaeha Kung KR Patent App. 1,020,190,180,035, 2019 | | 2019 |
Jae-Joon KimProfessor, Seoul National UniversityVerified email at snu.ac.kr
