Mayler G. A. Martins
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Open cell library in 15nm FreePDK technology
M Martins, JM Matos, RP Ribas, A Reis, G Schlinker, L Rech, J Michelsen
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
Boolean factoring with multi-objective goals
MGA Martins, L Rosa, AB Rasmussen, RP Ribas, AI Reis
Computer Design (ICCD), 2010 IEEE International Conference on, 229-234, 2010
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead
IAC Gomes, MGA Martins, AI Reis, FL Kastensmidt
Microelectronics Reliability 55 (9-10), 2072-2076, 2015
Semi-custom ncl design with commercial eda frameworks: Is it possible?
M Moreira, A Neutzling, M Martins, A Reis, R Ribas, N Calazans
Asynchronous Circuits and Systems (ASYNC), 2014 20th IEEE International …, 2014
Factored forms for memristive material implication stateful logic
FS Marranghello, V Callegaro, MGA Martins, AI Reis, RP Ribas
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR
IAC Gomes, M Martins, A Reis, FL Kastensmidt
Test Symposium (LATS), 2015 16th Latin-American, 1-6, 2015
Methodology for achieving best trade-off of area and fault masking coverage in ATMR
I Gomes, M Martins, F Lima Kastensmidt, A Reis, R Ribas, SP Novales
Test Workshop-LATW, 2014 15th Latin American, 1-6, 2014
Synthesis of threshold logic gates to nanoelectronics
A Neutzling, MGA Martins, RP Ribas, A Reis
Integrated Circuits and Systems Design (SBCCI), 2013 26th Symposium on, 1-6, 2013
Functional composition: A new paradigm for performing logic synthesis
MGA Martins, RP Ribas, AI Reis
Quality Electronic Design (ISQED), 2012 13th International Symposium on, 236-242, 2012
KL-cut based digital circuit remapping
L Machado, M Martins, V Callegaro, RP Ribas, A Reis
NORCHIP, 2012, 1-4, 2012
A Simple and Effective Heuristic Method for Threshold Logic Identification
A Neutzling, MGA Martins, V Callegaro, AI Reis, RP Ribas
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
Improving approximate-TMR using multi-objective optimization genetic algorithm
I Albandes, A Serrano-Cases, AJ Sánchez-Clemente, M Martins, ...
2018 IEEE 19th Latin-American Test Symposium (LATS), 1-6, 2018
Majority-based logic synthesis for nanometric technologies
MGA Martins, V Callegaro, FS Marranghello, RP Ribas, AI Reis
Nanotechnology (IEEE-NANO), 2014 IEEE 14th International Conference on, 256-261, 2014
Improved logic synthesis for memristive stateful logic using multi-memristor implication
FS Marranghello, V Callegaro, MGA Martins, AI Reis, RP Ribas
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 181-184, 2015
Spin diode network synthesis using functional composition
MGA Martins, FS Marranghello, JS Friedman, AV Sahakian, RP Ribas, ...
26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
Functional Composition Paradigm and Applications
MGA Martins, V Callegaro, L Machado, RP Ribas, AI Reis
Logic & Synthesis, 21th International Workshop on, 2012
Efficient method to compute minimum decision chains of Boolean functions
MGA Martins, V Callegaro, RP Ribas, AI Reis
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
A constructive approach for threshold logic circuit synthesis
A Neutzling, MGA Martins, RP Ribas, A Reis
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, 385-388, 2014
Iterative remapping respecting timing constraints
L Machado, MGA Martins, V Callegaro, RP Ribas, AI Reis
VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, 236-241, 2013
Design of approximate-TMR using approximate library and heuristic approaches
I Albandes, A Serrano-Cases, M Martins, A Martínez-Álvarez, ...
Microelectronics Reliability 88, 898-902, 2018
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