Scalable pattern matching for high speed networks CR Clark, DE Schimmel 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2004 | 518 | 2004 |
Efficient reconfigurable logic circuits for matching complex network intrusion detection patterns CR Clark, DE Schimmel International Conference on Field Programmable Logic and Applications, 956-959, 2003 | 203 | 2003 |
A hardware platform for network intrusion detection and prevention CR Clark, W Lee, DE Schimmel, D Contis, M Koné, A Thomas Proceedings of the 3rd Workshop on Network Processors and Applications (NP3), 2005 | 122 | 2005 |
Power constrained design of multiprocessor interconnection networks CS Patel, SM Chai, S Yalamanchili, DE Schimmel Proceedings International Conference on Computer Design VLSI in Computers …, 1997 | 113 | 1997 |
Design of efficient FPGA circuits for matching complex patterns in network intrusion detection systems CR Clark, DE Schimmel Electrical and Computer Engineering, Georgia Institute of Technology, 2003 | 99 | 2003 |
A Unified Model of Pattern-Matching Circuit Architectures C Clark, DE Schimmel Tech Report GIT-CERCS-05-20, 2005 | 83 | 2005 |
Ariadne—an adaptive router for fault-tolerant multicomputers JD Allen, PT Gaughan, DE Schimmel, S Yalamanchili ACM SIGARCH Computer Architecture News 22 (2), 278-288, 1994 | 64 | 1994 |
TCP-stream reassembly and state tracking in hardware M Necker, D Contis, D Schimmel Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom …, 2002 | 63 | 2002 |
Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks PT Gaughan, BV Dao, S Yalamanchili, DE Schimmel IEEE Transactions on Computers 45 (6), 651-665, 1996 | 59 | 1996 |
Issues in the design of high performance SIMD architectures JD Allen, DE Schimmel IEEE Transactions on Parallel and Distributed Systems 7 (8), 818-829, 1996 | 44 | 1996 |
A pattern-matching co-processor for network intrusion detection systems CR Clark, DE Schimmel Proceedings. 2003 IEEE International Conference on Field-Programmable …, 2003 | 36 | 2003 |
A novel low-cost approach to MCM interconnect test BC Kim, A Chatterjee, M Swaminathan, DE Schimmel Proceedings of 1995 IEEE International Test Conference (ITC), 184-192, 1995 | 28 | 1995 |
A new systolic array for the singular value decomposition DE Schimmel, FT Luk Proceedings of the fourth MIT conference on Advanced research in VLSI, 205-217, 1986 | 27 | 1986 |
An asynchronous architecture for modeling intersegmental neural communication GN Patel, MS Reid, DE Schimmel, SP DeWeerth IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (2), 97-110, 2006 | 25 | 2006 |
Energy-efficient network memory for ubiquitous devices JB Fryman, CM Huneycutt, HH Lee, KM Mackenzie, DE Schimmel IEEE Micro 23 (5), 60-70, 2003 | 24 | 2003 |
An FPGA-based network intrusion detection system with on-chip network interfaces CR Clark, CD Ulmer, DE Schimmel International journal of electronics 93 (6), 403-420, 2006 | 21 | 2006 |
Early analysis of cost/performance trade-offs in MCM systems V Garg, DJ Stogner, C Ulmer, DE Schimmel, C Dislis, S Yalamanchili, ... IEEE Transactions on Components, Packaging, and Manufacturing Technology …, 1997 | 21 | 1997 |
A novel test technique for MCM substrates B Kim, M Swaminathan, A Chatterjee, D Schimmel IEEE Transactions on Components, Packaging, and Manufacturing Technology …, 1997 | 21 | 1997 |
Power/performance trade-offs for direct networks CS Patel, SM Chai, S Yalamanchili, DE Schimmel Parallel Computer Routing and Communication: Second International Workshop …, 1998 | 18 | 1998 |
A VLSI architecture for modeling intersegmental coordination SP DeWeerth, GN Patel, MF Simoni, DE Schimmel, RL Calabrese Proceedings Seventeenth Conference on Advanced Research in VLSI, 182-200, 1997 | 18 | 1997 |