Shih-Lien Lu (Linus)
Shih-Lien Lu (Linus)
Director, TSMC
Verified email at tsmc.com - Homepage
Title
Cited by
Cited by
Year
Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance
KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ...
IEEE Journal of Solid-State Circuits 44 (1), 49-63, 2008
3742008
Trading off cache capacity for reliability to enable low voltage operation
C Wilkerson, H Gao, AR Alameldeen, Z Chishti, M Khellah, SL Lu
ACM SIGARCH computer architecture news 36 (3), 203-214, 2008
3062008
A 45 nm resilient microprocessor core for dynamic variation tolerance
KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ...
IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2010
2802010
Reducing cache power with low-cost, multi-bit error-correcting codes
C Wilkerson, AR Alameldeen, Z Chishti, W Wu, D Somasekhar, S Lu
Proceedings of the 37th annual international symposium on Computer …, 2010
2422010
Speeding up processing with approximation circuits
SL Lu
Computer 37 (3), 67-73, 2004
2352004
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
MT Chang, P Rosenfeld, SL Lu, B Jacob
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
2282013
Coming challenges in microarchitecture and architecture
R Ronen, A Mendelson, K Lai, SL Lu, F Pollack, JP Shen
Proceedings of the IEEE 89 (3), 325-340, 2001
2022001
RAMP: Research accelerator for multiple processors
J Wawrzynek, D Patterson, M Oskin, SL Lu, C Kozyrakis, JC Hoe, D Chiou, ...
IEEE micro 27 (2), 46-57, 2007
2002007
Improving cache lifetime reliability at ultra-low voltages
Z Chishti, AR Alameldeen, C Wilkerson, W Wu, SL Lu
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
1832009
Energy-efficient cache design using variable-strength error-correcting codes
AR Alameldeen, I Wagner, Z Chishti, W Wu, C Wilkerson, SL Lu
ACM SIGARCH Computer Architecture News 39 (3), 461-472, 2011
1762011
Floating-body dynamic random access memory and method of fabrication in tri-gate technology
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,098,507, 2006
1662006
STTRAM SCALING AND RETENTION FAILURE.
H Naeimi, C Augustine, A Raychowdhury, SL Lu, J Tschanz
Intel Technology Journal 17 (1), 2013
1492013
Circuit techniques for dynamic variation tolerance
K Bowman, J Tschanz, C Wilkerson, SL Lu, T Karnik, V De, S Borkar
2009 46th ACM/IEEE Design Automation Conference, 4-7, 2009
1422009
Floating-body memory cell write
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,061,806, 2006
1222006
One-transistor and one-capacitor DRAM cell for logic process technology
SLL Lu, VK De
US Patent 6,359,802, 2002
1212002
Noise suppression for open bit line DRAM architectures
D Somasekhar, SL Lu, VK De
US Patent 6,721,222, 2004
1202004
Low-leakage MOS planar capacitors for use within DRAM storage cells
D Somasekhar, SLL Lu, VK De
US Patent 6,421,269, 2002
1192002
Bloom filtering cache misses for accurate data speculation and prefetching
JK Peir, SC Lai, SL Lu, J Stark, K Lai
ACM International Conference on Supercomputing 25th Anniversary Volume, 347-356, 2002
1152002
Floating-body dynamic random access memory with purge line
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,002,842, 2006
1102006
Method and apparatus to generate a reference value in a memory array
D Somasekhar, Y Ye, MM Khellah, F Paillet, SH Tang, A Keshavarzi, ...
US Patent 6,952,376, 2005
1092005
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Articles 1–20