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Sung Kyu Lim
Sung Kyu Lim
Verified email at ece.gatech.edu - Homepage
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Cited by
Year
3D-MAPS: 3D massively parallel processor with stacked memory
DH Kim, K Athikulwongse, M Healy, M Hossain, M Jung, I Khorosh, ...
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 …, 2012
388*2012
A study of through-silicon-via impact on the 3D stacked IC layout
DH Kim, K Athikulwongse, SK Lim
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
3382009
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
M Jung, J Mitra, DZ Pan, SK Lim
Communications of the ACM 57 (1), 107-115, 2014
2222014
Edge separability-based circuit clustering with application to multilevel circuit partitioning
J Cong, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004
191*2004
Design and CAD methodologies for low power gate-level monolithic 3D ICs
SA Panth, K Samadi, Y Du, SK Lim
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
185*2014
Multiobjective microarchitectural floorplanning for 2-D and 3-D ICs
M Healy, M Vittes, M Ekpanyapong, CS Ballapuram, SK Lim, HHS Lee, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
182*2006
TSV stress aware timing analysis with applications to 3D-IC layout optimization
JS Yang, K Athikulwongse, YJ Lee, SK Lim, DZ Pan
Proceedings of the 47th Design Automation Conference, 803-806, 2010
162*2010
Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs
X Zhao, J Minz, SK Lim
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2010
159*2010
Thermal characterization of interlayer microfluidic cooling of three-dimensional integrated circuits with nonuniform heat flux
YJ Kim, YK Joshi, AG Fedorov, YJ Lee, SK Lim
1402010
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system
M Cho, C Liu, DH Kim, SK Lim, S Mukhopadhyay
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 694-697, 2010
138*2010
3D floorplanning with thermal vias
E Wong, SK Lim
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
1372006
Physical design for 3D system on package
SK Lim
IEEE Design & Test of Computers 22 (6), 532-539, 2005
1272005
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
K Athikulwongse, A Chakraborty, JS Yang, DZ Pan, SK Lim
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 669-674, 2010
1252010
A design tradeoff study with monolithic 3D integration
C Liu, SK Lim
Thirteenth International Symposium on Quality Electronic Design (ISQED), 529-536, 2012
1222012
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
C Liu, T Song, J Cho, J Kim, J Kim, SK Lim
Proceedings of the 48th Design Automation Conference, 783-788, 2011
1212011
Pre-bond testable low-power clock tree design for 3D stacked ICs
X Zhao, DL Lewis, HHS Lee, SK Lim
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
121*2009
Multiway partitioning with pairwise movement
J Cong, SK Lim
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998
1031998
Physical planning with retiming
J Cong, SK Lim
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000
1022000
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
SK Lim, D Xu, J Cong, P Li, T Shibuya
1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997
1021997
Fast and accurate analytical modeling of through-silicon-via capacitive coupling
DH Kim, S Mukhopadhyay, SK Lim
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2011
1002011
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Articles 1–20