Jan Moritz Joseph
Jan Moritz Joseph
CEO at RooflineAI & Reserach at RWTH Aachen
Verified email at - Homepage
Cited by
Cited by
A systematic methodology for characterizing scalability of DNN accelerators using SCALE-sim
A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna
2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories
F Staudigl, H Al Indari, D Schön, D Sisejkovic, F Merchant, JM Joseph, ...
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs
JM Joseph, C Blochwitz, A García-Ortiz, T Pionteck
Microprocessors and Microsystems 48, 36-47, 2017
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures
JM Joseph, L Bamberg, D Ermel, BR Perjikolaei, A Drewes, A García-Ortiz, ...
IEEE Access 7, 135145-135163, 2019
An FPGA-based prototyping framework for Networks-on-Chip
T Drewes, JM Joseph, T Pionteck
2017 International Conference on ReConFigurable Computing and FPGAs …, 2017
A cycle-accurate network-on-chip simulator with support for abstract task graph modeling
JM Joseph, T Pionteck
2014 International Symposium on System-on-Chip (SoC), 1-6, 2014
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs
JM Joseph, L Bamberg, I Hajjar, BR Perjikolaei, A García-Ortiz, T Pionteck
ACM Transactions on Modeling and Computer Simulation (TOMACS) 32 (1), 1-21, 2021
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
JM Joseph, A Samajdar, L Zhu, R Leupers, SK Lim, T Pionteck, T Krishna
2021 22nd International Symposium on Quality Electronic Design (ISQED), 60-66, 2021
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models
D Passaretti, JM Joseph, T Pionteck
2019 International Conference on Field-Programmable Technology (ICFPT), 279-282, 2019
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
JM Joseph, S Wrieden, C Blochwitz, A García-Oritz, T Pionteck
2016 11th International Symposium on Reconfigurable Communication-centric …, 2016
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
JM Joseph, M Mey, K Ehlers, C Blochwitz, T Winker, T Pionteck
2017 International Conference on ReConFigurable Computing and FPGAs …, 2017
AIrchitect: Automating Hardware Architecture and Mapping Optimization
A Samajdar, JM Joseph, T Krishna
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels
L Bamberg, JM Joseph, R Schmidt, T Pionteck, A García-Ortiz
2018 28th International Symposium on Power and Timing Modeling, Optimization …, 2018
Adaptive allocation of default router paths in Network-on-Chips for latency reduction
JM Joseph, C Blochwitz, T Pionteck
2016 International Conference on High Performance Computing & Simulation …, 2016
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases
C Blochwitz, JM Joseph, R Backasch, T Pionteck, S Werner, D Heinrich, ...
2015 International Conference on ReConFigurable Computing and FPGAs …, 2015
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation
F Staudigl, KJX Sturm, M Bartel, T Fetz, D Sisejkovic, JM Joseph, ...
2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI
JM Joseph, MS Baloglu, Y Pan, R Leupers, L Bamberg
Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip …, 2021
Hardware-Accelerated radix-tree based string sorting for big data applications
C Blochwitz, J Wolff, JM Joseph, S Werner, D Heinrich, S Groppe, ...
Architecture of Computing Systems-ARCS 2017: 30th International Conference …, 2017
Optimising operator sets for analytical database processing on FPGAs
A Drewes, JM Joseph, B Gurumurthy, D Broneske, G Saake, T Pionteck
International Symposium on Applied Reconfigurable Computing, 30-44, 2020
Simulation environment for link energy estimation in networks-on-chip with virtual channels
JM Joseph, L Bamberg, I Hajjar, R Schmidt, T Pionteck, A Garcia-Ortiz
Integration 68, 147-156, 2019
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