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Bradley A. Minch
Bradley A. Minch
Professor of Electrical and Computer Engineering, Franklin W. Olin College of Engineering
Verified email at olin.edu - Homepage
Title
Cited by
Cited by
Year
A single-transistor silicon synapse
C Diorio, P Hasler, A Minch, CA Mead
IEEE transactions on Electron Devices 43 (11), 1972-1980, 1996
3951996
A CMOS programmable analog memory-cell array using floating-gate circuits
RR Harrison, JA Bragg, P Hasler, BA Minch, SP Deweerth
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
1532001
Design of a CMOS potentiostat circuit for electrochemical detector arrays
S Ayers, KD Gillis, M Lindau, BA Minch
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (4), 736-744, 2007
1392007
Translinear circuits using subthreshold floating-gate MOS transistors
BA Minch, C Diorio, P Hasler, CA Mead
Analog Integrated Circuits and Signal Processing 9, 167-179, 1996
1361996
An autozeroing floating-gate amplifier
P Hasler, BA Minch, C Diorio
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
1332001
Single transistor learning synapses
P Hasler, C Diorio, B Minch, C Mead
Advances in neural information processing systems 7, 1994
1311994
Asynchronous Binaural Spatial Audition Sensor With 2644 Channel Output
SC Liu, A van Schaik, BA Minch, T Delbruck
IEEE transactions on biomedical circuits and systems 8 (4), 453-464, 2013
1282013
A high-resolution non-volatile analog memory cell
C Diorio, S Mahajan, P Hasler, B Minch, C Mead
1995 IEEE International Symposium on Circuits and Systems (ISCAS) 3, 2233-2236, 1995
1171995
Adaptive circuits using pFET floating-gate devices
P Hasler, BA Minch, C Diorio
Proceedings 20th Anniversary Conference on Advanced Research in VLSI, 215-229, 1999
1161999
Event-based 64-channel binaural silicon cochlea with Q enhancement mechanisms
SC Liu, A Van Schaik, BA Minch, T Delbruck
2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2027-2030, 2010
1092010
Parallel recording of neurotransmitters release from chromaffin cells using a 10× 10 CMOS IC potentiostat array with on-chip working electrodes
BN Kim, AD Herbst, SJ Kim, BA Minch, M Lindau
Biosensors and Bioelectronics 41, 736-744, 2013
1022013
A floating-gate MOS learning array with locally computed weight updates
C Diorio, P Hasler, BA Minch, CA Mead
IEEE Transactions on Electron Devices 44 (12), 2281-2289, 1997
931997
A physical compact model of DG MOSFET for mixed-signal circuit applications-part I: model description
G Pei, W Ni, AV Kammula, BA Minch, ECC Kan
IEEE Transactions on Electron Devices 50 (10), 2135-2143, 2003
812003
A low-voltage MOS cascode bias circuit for all current levels
BA Minch
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat …, 2002
752002
Autozeroing floating gate amplifier
BA Minch, PE Hasler, CJ Diorio, CA Mead
US Patent 5,875,126, 1999
711999
Semiconductor structure for long term learning
CJ Diorio, PE Hasler, BA Minch, CA Mead
US Patent 5,627,392, 1997
671997
Three-terminal silicon synaptic device
CJ Diorio, PE Hasler, BA Minch, CA Mead
US Patent 5,825,063, 1998
661998
Continuous-time feedback in floating-gate MOS circuits
P Hasler
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
632001
Floating-gate devices: they are not just for digital memories any more
P Hasler, BA Minch, C Diorio
1999 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 388-391, 1999
581999
A complementary pair of four-terminal silicon synapses
C Diorio, P Hasler, BA Minch, C Mead
Analog Integrated Circuits and Signal Processing 13, 153-166, 1997
571997
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