Yuan Xie

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Vijaykrishnan NarayananRobert Noll Chair Professor at The Pennsylvania State UniversityVerified email at cse.psu.edu
Xiangyu DongStaff Software Engineer, GoogleVerified email at acm.org
Yu Wang(汪玉)Department of Electronic Engineering, Tsinghua University, ChinaVerified email at mail.tsinghua.edu.cn
Cong XuResearch Scientist, Hewlett Packard LabsVerified email at hpe.com
Shuangchen LiResearch Scientist, DAMO Academy, Alibaba GroupVerified email at alibaba-inc.com
Guangyu SunCenter for Energy Efficient Computing and Applications, Peking UniversityVerified email at pku.edu.cn
Mary Jane (Janie) IrwinEmerita Evan Pugh University Professor, CSE, Penn State UniversityVerified email at cse.psu.edu
Jishen ZhaoAssociate Professor at University of California, San DiegoVerified email at ucsd.edu
Huazhong YangProfessor of Electronics Engineering, Tsinghua UniversityVerified email at tsinghua.edu.cn
Dimin NiuComputing Technology Lab, Alibaba DAMO AcademyVerified email at alibaba-inc.com
Lei Deng (邓磊)Assistant Professor at Tsinghua UniversityVerified email at mail.tsinghua.edu.cn
Tao ZhangAlibaba DAMO AcademyVerified email at alibaba-inc.com
Yiran ChenProfessor, Electrical and Computer Engineering, Duke UniversityVerified email at duke.edu
Marilyn WolfKoch Professor of Engineering and CSE ChairVerified email at unl.edu
Xing HuInstitute of Computing Technology, Chinese Academy of SciencesVerified email at ict.ac.cn
Mahmut KandemirPennsylvania State UniversityVerified email at psu.edu
Yongpan LiuProfessor @ Tsinghua UniversityVerified email at tsinghua.edu.cn
Guoqi LiAssociate Professor, Tsinghua University, Beijing, P.R. ChinaVerified email at mail.tsinghua.edu.cn
Jack SampsonAssociate Professor, Pennsylvania State UniversityVerified email at psu.edu
Yibo ChenPh.D. of Computer Engineering, Penn State UniversityVerified email at cse.psu.edu

Yuan Xie

Professor of University of California at Santa Barbara

Verified email at ece.ucsb.edu - Homepage

Computer Architecture VLSI EDA CAD Embedded Systems


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Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory X Dong, C Xu, Y Xie, NP Jouppi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012	961	2012
Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory P Chi, S Li, C Xu, T Zhang, J Zhao, Y Liu, Y Wang, Y Xie ACM SIGARCH Computer Architecture News 44 (3), 27-39, 2016	846	2016
Design and management of 3D chip multiprocessors using network-in-memory F Li, C Nicopoulos, T Richardson, Y Xie, V Narayanan, M Kandemir 33rd International Symposium on Computer Architecture (ISCA'06), 130-141, 2006	510	2006
Design space exploration for 3D architectures Y Xie, GH Loh, B Black, K Bernstein ACM Journal on Emerging Technologies in Computing Systems (JETC) 2 (2), 65-103, 2006	501	2006
A novel architecture of the 3D stacked MRAM L2 cache for CMPs G Sun, X Dong, Y Xie, J Li, Y Chen 2009 IEEE 15th International Symposium on High Performance Computer …, 2009	493	2009
Hybrid cache architecture with disparate memory technologies X Wu, J Li, L Zhang, E Speight, R Rajamony, Y Xie ACM SIGARCH computer architecture news 37 (3), 34-45, 2009	435	2009
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement X Dong, X Wu, G Sun, Y Xie, H Li, Y Chen 2008 45th ACM/IEEE Design Automation Conference, 554-559, 2008	382	2008
Processor design in 3D die-stacking technologies GH Loh, Y Xie, B Black Ieee Micro 27 (3), 31-48, 2007	378	2007
A novel dimensionally-decomposed router for on-chip communication in 3D architectures J Kim, C Nicopoulos, D Park, R Das, Y Xie, V Narayanan, MS Yousif, ... Proceedings of the 34th annual international symposium on Computer …, 2007	354	2007
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs A Jog, AK Mishra, C Xu, Y Xie, V Narayanan, R Iyer, CR Das DAC Design Automation Conference 2012, 243-252, 2012	300	2012
MIRA: A multi-layered on-chip interconnect router architecture D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das 2008 International Symposium on Computer Architecture, 251-261, 2008	299	2008
Cambricon: An instruction set architecture for neural networks S Liu, Z Du, J Tao, D Han, T Luo, Y Xie, Y Chen, T Chen 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture …, 2016	286	2016
Overcoming the challenges of crossbar resistive memory architectures C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie 2015 IEEE 21st International Symposium on High Performance Computer …, 2015	264	2015
Design implications of memristor-based RRAM cross-point structures C Xu, X Dong, NP Jouppi, Y Xie 2011 Design, Automation & Test in Europe, 1-6, 2011	262	2011
Kiln: Closing the performance gap between systems with and without persistence support J Zhao, S Li, DH Yoon, Y Xie, NP Jouppi Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013	248	2013
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories S Li, C Xu, Q Zou, J Zhao, Y Lu, Y Xie Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016	245	2016
Interconnect and thermal-aware floorplanning for 3D microprocessors WL Hung, GM Link, Y Xie, N Vijaykrishnan, MJ Irwin 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-104, 2006	242	2006
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges LP Carloni, P Pande, Y Xie 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 93-102, 2009	219	2009
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs) X Dong, Y Xie 2009 Asia and South Pacific Design Automation Conference, 234-241, 2009	209	2009
DLAU: A scalable deep learning accelerator unit on FPGA C Wang, L Gong, Q Yu, X Li, Y Xie, X Zhou IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016	208	2016

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