| A designer's guide to asynchronous VLSI PA Beerel, RO Ozdag, M Ferretti Cambridge University Press, 2010 | 271 | 2010 |
| High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells M Ferretti, RO Ozdag, PA Beerel 10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004 | 146 | 2004 |
| Single-track asynchronous pipeline templates using 1-of-N encoding M Ferretti, PA Beerel Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 102 | 2002 |
| High performance asynchronous design using single-track full-buffer standard cells M Ferretti, PA Beerel IEEE Journal of Solid-State Circuits 41 (6), 1444-1454, 2006 | 61 | 2006 |
| Low swing signaling using a dynamic diode-connected driver M Ferretti, PA Beerel Proceedings of the 27th European Solid-State Circuits Conference, 369-372, 2001 | 43 | 2001 |
| Single-track asynchronous pipeline template M Ferretti University of Southern California, 2004 | 23 | 2004 |
| A Distributed Embedded System for Modular Self-Reconfigurable Robots A Seshadri, M Ferretti, A Castano, P Will ISI Technical Report ISI-TR-551, 2001 | 2 | 2001 |
| Copper Interconnects for High-Speed, Low-Power Static Memories A Sinha, S Singh, A Ajami, AR Ahmed, J Moon, M Ferretti, S Tugsinavsut, ... Semiconductor Research Corporation Design Contest, 2000 | 1 | 2000 |
Peter BeerelProfessor of Electrical and Computer Engineering, USCVerified email at usc.edu
Peter BeerelProfessor of Electrical and Computer Engineering, USCVerified email at usc.edu