Chiu-Wing Sham
Chiu-Wing Sham
Verified email at auckland.ac.nz
Title
Cited by
Cited by
Year
Routability-driven floorplanner with buffer block planning
CW Sham, EFY Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
602003
A bitstream reconfigurable FPGA implementation of the WSAT algorithm
PHW Leong, CW Sham, WC Wong, HY Wong, WS Yuen, MP Leong
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1), 197-201, 2001
412001
A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes
CW Sham, X Chen, FCM Lau, Y Zhao, WM Tam
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (7), 1857-1869, 2013
332013
Fast power-and slew-aware gated clock tree synthesis
J Lu, WK Chow, CW Sham
IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011
292011
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach
WK Chow, L Li, EFY Young, CW Sham
Integration 47 (1), 105-114, 2014
222014
A dual-MST approach for clock network synthesis
J Lu, WK Chow, CW Sham, EFY Young
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 467-473, 2010
222010
Congestion prediction in early stages
C Sham, EFY Young
Proceedings of the 2005 international workshop on System level interconnect …, 2005
222005
A 3.0 Gb/s throughput hardware-efficient decoder for cyclically-coupled QC-LDPC codes
Q Lu, J Fan, CW Sham, WM Tam, FCM Lau
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (1), 134-145, 2016
202016
Congestion prediction in early stages of physical design
CW Sham, EFY Young, J Lu
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (1 …, 2009
172009
Optimal cell flipping in placement and floorplanning
C Sham, ERY Young, C Chu
2006 43rd ACM/IEEE Design Automation Conference, 1109-1114, 2006
172006
Congestion estimation with buffer planning in floorplan design
CW Sham, WC Wong, ERY Young
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
132002
A new clock network synthesizer for modern VLSI designs
J Lu, WK Chow, CW Sham
Integration 45 (2), 121-131, 2012
122012
LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search
J Lu, CW Sham
International Symposium on Quality Electronic Design (ISQED), 231-238, 2013
112013
A layered QC-LDPC decoder architecture for high speed communication system
CW Sham, X Chen, WM Tam, Y Zhao, FCM Lau
2012 IEEE Asia Pacific Conference on Circuits and Systems, 475-478, 2012
112012
Efficient decoding of QC-LDPC codes using GPUs
Y Zhao, X Chen, CW Sham, WM Tam, FCM Lau
International Conference on Algorithms and Architectures for Parallel …, 2011
92011
Rapid prototyping of multi-mode QC-LDPC decoder for 802.11 n/ac standard
Q Lu, CW Sham, FCM Lau
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 19-20, 2016
72016
A high throughput Gaussian noise generator
Q Lu, J Fan, CW Sham, FCM Lau
2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 117-120, 2014
72014
Congestion prediction in floorplanning
C Sham, EFY Young
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
72005
A parallel-routing network for reliability inferences of single-parity-check decoder
Q Lu, Z Shen, CW Sham, FCM Lau
2015 International Conference on Advanced Technologies for Communications …, 2015
62015
Congestion-oriented approach in placement for analog and mixed-signal circuits
H Zhou, CW Sham, H Yao
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013), 97-102, 2013
62013
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Articles 1–20