Chiu-Wing Sham
Chiu-Wing Sham
Verified email at auckland.ac.nz
Title
Cited by
Cited by
Year
Routability-driven floorplanner with buffer block planning
CW Sham, EFY Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
682003
A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes
CW Sham, X Chen, FCM Lau, Y Zhao, WM Tam
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (7), 1857-1869, 2013
46*2013
A bitstream reconfigurable FPGA implementation of the WSAT algorithm
PHW Leong, CW Sham, WC Wong, HY Wong, WS Yuen, MP Leong
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1), 197-201, 2001
442001
Fast power-and slew-aware gated clock tree synthesis
J Lu, WK Chow, CW Sham
IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011
332011
A 3.0 Gb/s throughput hardware-efficient decoder for cyclically-coupled QC-LDPC codes
Q Lu, J Fan, CW Sham, WM Tam, FCM Lau
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (1), 134-145, 2016
30*2016
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach
WK Chow, L Li, EFY Young, CW Sham
Integration 47 (1), 105-114, 2014
262014
Congestion prediction in early stages
C Sham, EFY Young
Proceedings of the 2005 international workshop on System level interconnect …, 2005
242005
A dual-MST approach for clock network synthesis
J Lu, WK Chow, CW Sham, EFY Young
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 467-473, 2010
222010
Congestion prediction in early stages of physical design
CW Sham, EFY Young, J Lu
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (1 …, 2009
21*2009
LMgr: A low-memory global router with dynamic topology update and bending-aware optimum path search
J Lu, CW Sham
International Symposium on Quality Electronic Design (ISQED), 231-238, 2013
182013
A layered QC-LDPC decoder architecture for high speed communication system
CW Sham, X Chen, WM Tam, Y Zhao, FCM Lau
2012 IEEE Asia Pacific Conference on Circuits and Systems, 475-478, 2012
182012
A new clock network synthesizer for modern vlsi designs
J Lu, WK Chow, CW Sham
Integration 45 (2), 121-131, 2012
182012
Optimal cell flipping in placement and floorplanning
C Sham, ERY Young, C Chu
2006 43rd ACM/IEEE Design Automation Conference, 1109-1114, 2006
182006
Congestion estimation with buffer planning in floorplan design
CW Sham, WC Wong, ERY Young
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
182002
Efficient decoding of QC-LDPC codes using GPUs
Y Zhao, X Chen, CW Sham, WM Tam, FCM Lau
International Conference on Algorithms and Architectures for Parallel …, 2011
122011
A parallel-routing network for reliability inferences of single-parity-check decoder
Q Lu, Z Shen, CW Sham, FCM Lau
2015 International Conference on Advanced Technologies for Communications …, 2015
112015
Fixed-point implementation of convolutional neural networks for image classification
CY Lo, FCM Lau, CW Sham
2018 International Conference on Advanced Technologies for Communications …, 2018
92018
Optimized layer architecture for layered LDPC code decoder
L Ma, CW Sham
2018 International Conference on Advanced Technologies for Communications …, 2018
82018
Rapid prototyping of multi-mode QC-LDPC decoder for 802.11 n/ac standard
Q Lu, CW Sham, FCM Lau
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 19-20, 2016
82016
A high throughput Gaussian noise generator
Q Lu, J Fan, CW Sham, FCM Lau
2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 117-120, 2014
72014
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Articles 1–20