Mu-Tien Chang
Cited by
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Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
MT Chang, P Rosenfeld, SL Lu, B Jacob
2013 IEEE 19th International Symposium on High Performance Computerá…, 2013
DRAM refresh mechanisms, penalties, and trade-offs
IS Bhati, MT Chang, Z Chishti, SL Lu, B Jacob
IEEE Transactions on Computers 65 (1), 108-121, 2016
An Integrated Simulation Infrastructure for the Entire Memory Hierarchy: Cache, DRAM, Nonvolatile Memory, and Disk
J Stevens, P Tschirhart, MT Chang, I Bhati, P Enns, J Greensky, Z Chisti, ...
Intel« Technology Journal 17 (1), 2013
System and method for using a truth table graphical function in a statechart
RO Aberg, V Raghavan, Y Ren
US Patent 8,798,971, 2014
A fully-differential subthreshold sram cell with auto-compensation
MT Chang, W Hwang
APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1771-1774, 2008
A 65nm low power 2T1D embedded DRAM with leakage current reduction
MT Chang, PT Huang, W Hwang
2007 IEEE International SOC Conference, 207-210, 2007
Method of spatial monitoring and controlling corrosion of superheater and reheater tubes
D Eden, B Breen, J Gabrielson, R Schrecengost, M Valvano
US Patent App. 10/114,560, 2003
Vehicle suspension system
CC Anderson, RC Nelson
US Patent 6,959,936, 2005
Thyristor-based device with trench dielectric material
A Horch, S Robins
US Patent 6,835,997, 2004
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control
MT Chang, PT Huang, W Hwang
2008 IEEE International SOC Conference, 175-178, 2008
Multi-cell structure for non-volatile resistive memory
D Niu, MT Chang, H Zheng
US Patent App. 15/136,872, 2017
Reliability-aware memory partitioning mechanisms for future memory technologies
D Niu, MT Chang, H Zheng
US Patent 9,696,923, 2017
Transaction-based hybrid memory module
MT Chang, H Zheng, D Niu
US Patent App. 14/947,145, 2017
System architecture with memory channel DRAM FPGA module
H Zheng, MT Chang
US Patent 10,013,212, 2018
System and method for operating a drr-compatible asynchronous memory module
SY Lim, MT Chang, D Niu, H Zheng, KIM Indong
US Patent App. 15/285,423, 2017
Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache
T Stocksdale, MT Chang, H Zheng, F Mueller
Proceedings of the 2nd Joint International Workshop on Parallel Data Storageá…, 2017
3-d stacked memory with reconfigurable compute logic
MT Chang, P Gera, D Niu, H Zheng
US Patent App. 15/143,248, 2017
FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration
KT Malladi, MT Chang, J Ping, H Zheng
2015 IEEE 23rd International Symposium on Modeling, Analysis, and Simulationá…, 2015
Smart-channel: learning-capable television channel changing apparatus, system and method
DB Macrae, KS Hancock
US Patent 6,870,579, 2005
Asynchronous communication protocol compatible with synchronous DDR protocol
D Niu, MT Chang, H Zheng, SY Lim, KIM Indong, J Choi, C Hanson
US Patent 10,621,119, 2020
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