| Deep learning binary neural network on an FPGA Y Zhou, S Redkar, X Huang 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 39 | 2017 |
| A system-on-chip FPGA design for real-time traffic signal recognition system Y Zhou, Z Chen, X Huang 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1778-1781, 2016 | 28 | 2016 |
| A pipeline architecture for traffic sign classification on an FPGA Y Zhou, Z Chen, X Huang 2015 IEEE international symposium on circuits and systems (ISCAS), 950-953, 2015 | 16 | 2015 |
| FPGA design for PCANet deep learning network Y Zhou, W Wang, X Huang 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 15 | 2015 |
| Roadnet: An 80-mw hardware accelerator for road detection Y Zhou, Y Lyu, X Huang IEEE Embedded Systems Letters 11 (1), 21-24, 2018 | 7 | 2018 |
| A 20 TOp/s/W binary neural network accelerator X Huang, Y Zhou 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 4 | 2019 |
| An FPGA prototype of dual link algorithm for MIMO interference network M Zhou, X Huang, Y Zhou, X Li, Y Liu 2017 IEEE International Conference on Acoustics, Speech and Signal …, 2017 | 2 | 2017 |
| Computer Vision System-On-Chip Designs for Intelligent Vehicles Y Zhou Computer 2018, 04-24, 2018 | 1 | 2018 |
| VLSI design of a power-efficient object detector using PCANet Y Zhou, X Huang IEICE Electronics Express 15 (12), 20180396-20180396, 2018 | | 2018 |
