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Geir Eide
Geir Eide
Siemens Digital Industries Software
Verified email at mentor.com
Title
Cited by
Cited by
Year
Embedded deterministic test for low cost manufacturing test
J Rajski, J Tyszer, M Kassab, N Mukherjee, R Thompson, KH Tsai, ...
Proceedings. International Test Conference, 301-310, 2002
4822002
Age, body composition, aerobic fitness and health condition as risk factors for musculoskeletal injuries in conscripts
T Heir, G Eide
Scandinavian journal of medicine & science in sports 6 (4), 222-227, 1996
1371996
Injury proneness in infantry conscripts undergoing a physical training programme: smokeless tobacco use, higher age, and low levels of physical fitness are risk factors
T Heir, G Eide
Scandinavian journal of medicine & science in sports 7 (5), 304-311, 1997
1331997
Experiences with Layout-Aware Diagnosis–A Case Study
YJ Chang, MT Pang, M Brennan, A Man, M Keim, G Eide, B Benware, ...
Electronic Device Failure Analysis 12 (12), 12-18, 2010
442010
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
JF Côté, M Kassab, W Janiszewski, R Rodrigues, R Meier, B Kaczmarek, ...
2020 IEEE International Test Conference (ITC), 1-10, 2020
182020
Automatic identification of yield limiting layout patterns using root cause deconvolution on volume scan diagnosis data
WT Cheng, R Klingenberg, B Benware, W Yang, M Sharma, G Eide, ...
2017 IEEE 26th Asian Test Symposium (ATS), 219-224, 2017
132017
The changing role of diagnosis in yield analysis
G Eide, D Appello
Test & Measurement World, 43-49, 2010
92010
Avoid throwing darts at a black hole by using Diagnosis-Driven Yield Analysis
G Eide
Solid State Technology 53 (7), 24-27, 2010
82010
Key impediments to DFT-focused test and how to overcome them
K Posse, G Eide
International Test Conference, 503-511, 2003
72003
Deriving feature fail rate from silicon volume diagnostics data
S Malik, T Herrmann, S Madhavan, R Desineni, C Schuermyer, G Eide
IEEE Design & Test 30 (4), 26-34, 2013
52013
Diagnosis of Scan Logic and Diagnosis Driven Failure Analysis
S Venkataraman, M Keim, G Eide
Microelectronics Failure Analysis: Desk Reference, 199, 2011
22011
Root Cause Deconvolution—The Next Step in Diagnosis Resolution Improvement
G Eide
White paper: http://www. mentor. com/products/siliconyield/techpubs, 0
2
Employing the stdf v4-2007 standard for scan test data logging
M Seuring, M Braun, A Ma, G Eide, K Yang, H Tang
IEEE Design & Test of Computers 29 (6), 91-99, 2012
12012
When good DFT goes bad: debugging broken scan chains
Y Huang, G Eide
Mentor Graphics 18, 2012
12012
Scan diagnostic analysis assists SoC fab debug/process monitoring
S Palosh, G Eide
Solid State Technology 54 (7), 22-24, 2011
12011
Leveraging Diagnosis for Yield Analysis
G Eide, D Appello
Design Automation Conference, Anaheim, CA, 13-18, 2010
12010
The Advancement of 1149.10
Y Huang, H Fu, B Deng, E Seng, M Hutner, JF Cote, G Eide
2021 IEEE International Test Conference in Asia (ITC-Asia), 1-1, 2021
2021
Identifying transistor-level yield limiters in the finFET era
G Eide, M Graphics
EE-Evaluation Engineering 56 (5), 18-20, 2017
2017
Noise cancellation: The new failure and yield analysis superpower
G Eide
SOLID STATE TECHNOLOGY 57 (4), 37-38, 2014
2014
The Value of Test for Semiconductor Yield Learning
G Eide
2012
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