A. Can Sitik
A. Can Sitik
Software Engineer, Intel Co.
Verified email at intel.com - Homepage
Title
Cited by
Cited by
Year
Design methodology for voltage-scaled clock distribution networks
C Sitik, W Liu, B Taskin, E Salman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016
242016
FinFET-based low-swing clocking
C Sitik, E Salman, L Filippini, SJ Yoon, B Taskin
ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (2), 1-20, 2015
202015
High performance low swing clock tree synthesis with custom D flip-flop design
C Sitik, L Filippini, E Salman, B Taskin
2014 IEEE Computer Society Annual Symposium on VLSI, 498-503, 2014
122014
Timing characterization of clock buffers for clock tree synthesis
C Sitik, S Lerner, B Taskin
2014 IEEE 32nd International Conference on Computer Design (ICCD), 230-236, 2014
112014
Skew-bounded low swing clock tree optimization
C Sitik, B Taskin
Proceedings of the 23rd ACM international conference on Great lakes …, 2013
112013
Enhanced level shifter for multi-voltage operation
W Liu, E Salman, C Sitik, B Taskin
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1442-1445, 2015
92015
A novel static D-flip-flop topology for low swing clocking
M Rathore, W Liu, E Salman, C Sitik, B Taskin
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 301-306, 2015
82015
Clock skew scheduling in the presence of heavily gated clock networks
W Liu, E Salman, C Sitik, B Taskin
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 283-288, 2015
72015
Multi-voltage domain clock mesh design
C Sitik, B Taskin
2012 IEEE 30th International Conference on Computer Design (ICCD), 201-206, 2012
72012
Multi-corner multi-voltage domain clock mesh design
C Sitik, B Taskin
Proceedings of the 23rd ACM international conference on Great lakes …, 2013
52013
Exploiting useful skew in gated low voltage clock trees
W Liu, E Salman, C Sitik, B Taskin
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2595-2598, 2016
42016
SLECTS: Slew-driven clock tree synthesis
W Liu, C Sitik, E Salman, B Taskin, S Sundareswaran, B Huang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (4), 864-874, 2019
32019
Circuits and algorithms to facilitate low swing clocking in nanoscale technologies
W Liu, E Salman, C Sitik, B Taskin, S Sundareswaran, B Huang
Proceedings of Semiconductor Research Corporation (SRC) TECHCON. SRC, 2015
22015
Iterative skew minimization for low swing clocks
C Sitik, B Taskin
Integration 47 (3), 356-364, 2014
22014
A microcontroller-based embedded system design course with PSoC3
C Sitik, P Nagvajara, B Taskin
2013 IEEE International Conference on Microelectronic Systems Education (MSE …, 2013
22013
Low Voltage Clock Tree Synthesis with Local Gate Clusters
C Sitik, W Liu, B Taskin, E Salman
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 99-104, 2019
12019
Technologies for node-degree based clustering of data sets
AC Sitik, A More
US Patent 10,452,717, 2019
2019
Slew-driven clock tree synthesis
WC Liu, E Salman, AC Sitik, B Taskin
US Patent 10,338,633, 2019
2019
Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits
B Taskin, AC Sitik
US Patent 9,773,079, 2017
2017
Design and automation of voltage-scaled clock networks
AC Sitik
Drexel University, 2015
2015
The system can't perform the operation now. Try again later.
Articles 1–20