| Performance optimization and analysis of blade designs under delay variability D Hand, HH Huang, B Cheng, Y Zhang, MT Moreira, M Breuer, ... 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015 | 14 | 2015 |
| Trading off area, yield and performance via hybrid redundancy in multi-core architectures Y Gao, Y Zhang, D Cheng, MA Breuer 2013 IEEE 31st VLSI Test Symposium (VTS), 1-6, 2013 | 14 | 2013 |
| Challenges in building an open-source flow from RTL to bundled-data design Y Zhang, H Cheng, D Chen, H Fu, S Agarwal, M Lin, B Peter 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems …, 2018 | 10 | 2018 |
| Design and analysis of testable mutual exclusion elements Y Zhang, LS Heck, MT Moreira, D Zar, M Breuer, NLV Calazans, ... 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015 | 7 | 2015 |
| Test margin and yield in bundled data and ring-oscillator based designs Y Zhang, H Zha, V Sahir, H Cheng, PA Beerel 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems …, 2017 | 5 | 2017 |
| Testable MUTEX design Y Zhang, LS Heck, MT Moreira, D Zar, MA Breuer, NLV Calazans, ... IEEE Transactions on Circuits and Systems I: Regular Papers 63 (8), 1188-1199, 2016 | 4 | 2016 |
| Dual-output LUT merging during FPGA technology mapping F Wang, L Zhu, J Zhang, L Li, Y Zhang, G Luo Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 3 | 2020 |
| Yield modelling and analysis of bundled data and ring‐oscillator based designs Y Zhang, J Li, H Cheng, H Zha, J Draper, PA Beerel IET Computers & Digital Techniques 13 (3), 262-272, 2019 | 1 | 2019 |
| Two-phase asynchronous to synchronous interfaces for an open-source bundled-data flow A Abdelhadi, D Chen, H Cheng, G Datta, Y Zhang, P Beerel, ... 25th IEEE International Symposium on Asynchronous Circuits and Systems-Fresh …, 2019 | 1 | 2019 |
