Chris Chu
Title
Cited by
Cited by
Year
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model
N Viswanathan, CCN Chu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
3302005
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
CP Chen, CCN Chu, DF Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
3121999
Handbook of algorithms for physical design automation
CJ Alpert, DP Mehta, SS Sapatnekar
CRC press, 2008
2342008
FLUTE: Fast lookup table based rectilinear steiner minimal tree algorithm for VLSI design
C Chu, YC Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
2192007
FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control
N Viswanathan, M Pan, C Chu
2007 Asia and South Pacific Design Automation Conference, 135-140, 2007
1832007
An efficient and effective detailed placement algorithm
M Pan, N Viswanathan, C Chu
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
1812005
A matrix synthesis approach to thermal placement
CCN Chu, DF Wong
Proceedings of the 1997 international symposium on Physical design, 163-168, 1997
1501997
FLUTE: fast lookup table based wirelength estimation technique
C Chu
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
1362004
FastRoute: A step to integrate global routing into placement
M Pan, C Chu
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
1342006
FastRoute 4.0: global router with efficient via minimization
Y Xu, Y Zhang, C Chu
2009 Asia and South Pacific Design Automation Conference, 576-581, 2009
1302009
FastRoute 2.0: A high-quality and efficient global router
M Pan, C Chu
2007 Asia and south pacific design automation conference, 250-255, 2007
1162007
Fitted Elmore delay: a simple and accurate interconnect delay model
AI Abou-Seido, B Nowak, C Chu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (7), 691-696, 2004
1162004
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
C Chu, YC Wong
Proceedings of the 2005 international symposium on Physical design, 28-35, 2005
972005
Twin binary sequences: a nonredundant representation for general nonslicing floorplan
EFY Young, CCN Chu, ZC Shen
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
932003
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
C Chu, DF Wong
ACM Transactions on Design Automation of Electronic Systems (TODAES) 6 (3 …, 2001
832001
RQL: Global placement via relaxed quadratic spreading and linearization
N Viswanathan, GJ Nam, CJ Alpert, P Villarrubia, H Ren, C Chu
Proceedings of the 44th annual Design Automation Conference, 453-458, 2007
782007
IPR: An integrated placement and routing algorithm
M Pan, C Chu
Proceedings of the 44th annual Design Automation Conference, 59-62, 2007
772007
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
CCN Chu, DF Wong
Proceedings of the 1997 international symposium on Physical design, 192-197, 1997
751997
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm
JZ Yan, C Chu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
702010
Efficient rectilinear Steiner tree construction with rectilinear blockages
Z Shen, CCN Chu, YM Li
2005 International Conference on Computer Design, 38-44, 2005
692005
The system can't perform the operation now. Try again later.
Articles 1–20