| Analyzing the impact of single-event-induced charge sharing in complex circuits S Pagliarini, F Kastensmidt, L Entrena, A Lindoso, E San Millan IEEE Transactions on Nuclear Science 58 (6), 2768-2775, 2011 | 54 | 2011 |
| A flexible online checking technique to enhance hardware trojan horse detectability by reliability analysis RS Chakraborty, S Pagliarini, J Mathew, SR Rajendran, MN Devi IEEE Transactions on Emerging Topics in Computing 5 (2), 260-270, 2017 | 53 | 2017 |
| Selective hardening methodology for combinational logic SN Pagliarini, LAB Naviner, JF Naviner 2012 13th latin American test workshop (LATW), 1-6, 2012 | 45 | 2012 |
| Constrained placement methodology for reducing SER under single-event-induced charge sharing effects L Entrena, A Lindoso, E San Millan, S Pagliarini, F Almeida, ... IEEE Transactions on Nuclear Science 59 (4), 811-817, 2012 | 40 | 2012 |
| A survey on split manufacturing: Attacks, defenses, and challenges TD Perez, S Pagliarini IEEE Access 8, 184013-184035, 2020 | 35 | 2020 |
| A fault tolerant approach to detect transient faults in microprocessors based on a non-intrusive reconfigurable hardware JR Azambuja, S Pagliarini, M Altieri, FL Kastensmidt, M Hubner, J Becker, ... IEEE Transactions on Nuclear Science 59 (4), 1117-1124, 2012 | 33 | 2012 |
| Exploring the feasibility of selective hardening for combinational logic SN Pagliarini, GG dos Santos, LAB Naviner, JF Naviner Microelectronics Reliability 52 (9-10), 1843-1847, 2012 | 27 | 2012 |
| An oscillatory neural network with programmable resistive synapses in 28 nm CMOS T Jackson, S Pagliarini, L Pileggi 2018 IEEE International Conference on Rebooting Computing (ICRC), 1-7, 2018 | 26 | 2018 |
| Exploring the limitations of software-based techniques in SEE fault coverage JR Azambuja, S Pagliarini, L Rosa, FL Kastensmidt Journal of Electronic Testing 27, 541-550, 2011 | 26 | 2011 |
| Latch-based logic locking J Sweeney, VM Zackriya, S Pagliarini, L Pileggi 2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020 | 24 | 2020 |
| A systematic study of lattice-based NIST PQC algorithms: From reference implementations to hardware accelerators M Imran, ZU Abideen, S Pagliarini arXiv preprint arXiv:2009.07091, 2020 | 20* | 2020 |
| A placement strategy for reducing the effects of multiple faults in digital circuits SN Pagliarini, D Pradhan 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 69-74, 2014 | 16 | 2014 |
| An open-source library of large integer polynomial multipliers M Imran, ZU Abideen, S Pagliarini 2021 24th International Symposium on Design and Diagnostics of Electronic …, 2021 | 14 | 2021 |
| An Area Aware Accelerator for Elliptic Curve Point Multiplication M Imran, S Pagliarini, M Rashid | 14 | 2020 |
| Side-channel trojan insertion-a practical foundry-side attack via ECO T Perez, M Imran, P Vaz, S Pagliarini 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 13 | 2021 |
| Snap: A novel hybrid method for circuit reliability assessment under multiple faults SN Pagliarini, AB Dhia, LAB Naviner, JF Naviner Microelectronics Reliability 53 (9-11), 1230-1234, 2013 | 12 | 2013 |
| Design space exploration of saber in 65nm ASIC M Imran, F Almeida, J Raik, A Basso, SS Roy, S Pagliarini Proceedings of the 5th Workshop on Attacks and Solutions in Hardware …, 2021 | 11 | 2021 |
| A probabilistic synapse with strained MTJs for spiking neural networks SN Pagliarini, S Bhuin, MM Isgenc, AK Biswas, L Pileggi IEEE Transactions on Neural Networks and Learning Systems 31 (4), 1113-1123, 2019 | 11 | 2019 |
| A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs AB Dhia, SN Pagliarini, LAB Naviner, H Mehrez, P Matherat Microelectronics Reliability 53 (9-11), 1189-1193, 2013 | 10 | 2013 |
| From FPGAs to obfuscated eASICs: Design and security trade-offs ZU Abideen, TD Perez, S Pagliarini 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 1-4, 2021 | 9 | 2021 |
