| A 23 mW, 73 dB dynamic range, 80 MHz BW continuous-time delta-sigma modulator in 20 nm CMOS S Ho, CL Lo, J Ru, J Zhao IEEE Journal of Solid-State Circuits 50 (4), 908-919, 2015 | 85 | 2015 |
| 15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS Y Dong, J Zhao, W Yang, T Caldwell, H Shibata, R Schreier, Q Meng, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 278-279, 2016 | 65 | 2016 |
| A 72 db-dr 465 mhz-bw continuous-time 1-2 mash adc in 28 nm cmos Y Dong, J Zhao, WW Yang, T Caldwell, H Shibata, Z Li, R Schreier, ... IEEE Journal of Solid-State Circuits 51 (12), 2917-2927, 2016 | 62 | 2016 |
| A 9-GS/s 1.125-GHz BW oversampling continuous-time pipeline ADC achieving− 164-dBFS/Hz NSD H Shibata, V Kozlov, Z Ji, A Ganesan, H Zhu, D Paterson, J Zhao, S Patil, ... IEEE Journal of Solid-State Circuits 52 (12), 3219-3234, 2017 | 60 | 2017 |
| Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS Y Dong, B Jose, Q Meng, J Zhao, W Yang, T Caldwell, H Shibata, Z Li, ... 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 24 | 2017 |
| Digital measurement of DAC timing mismatch error J Zhao, Q Meng, Y Dong, JB Silva US Patent 9,735,797, 2017 | 19 | 2017 |
| Adaptive digital quantization noise cancellation filters for mash ADCs Q Meng, H Shibata, RE Schreier, MS McCORMICK, Y Dong, JB Silva, ... US Patent 9,768,793, 2017 | 17 | 2017 |
| Dither injection for continuous-time MASH ADCS Y Dong, H Shibata, TC Caldwell, Z Li, J Zhao, JB Silva US Patent 9,838,031, 2017 | 14 | 2017 |
| Digital measurement of DAC switching mismatch error J Zhao US Patent 9,716,509, 2017 | 14 | 2017 |
| Estimation of digital-to-analog converter static mismatch errors J Zhao, RE Schreier, JB Silva, H Shibata, WW Yang, Y Dong US Patent 9,203,426, 2015 | 14 | 2015 |
| Background flash offset calibration in continuous-time delta-sigma ADCS Z Li, TC Caldwell, DN Alldred, Y Dong, PM Shrestha, J Zhao, H Shibata, ... US Patent 9,843,337, 2017 | 10 | 2017 |
| A− 89-dBc IMD3 DAC sub-system in a 465-MHz BW CT delta-sigma ADC using a power and area efficient calibration technique J Zhao, Y Dong, W Yang, H Shibata, P Shrestha, Z Li, T Caldwell, ... IEEE Transactions on Circuits and Systems II: Express Briefs 65 (7), 859-863, 2017 | 8 | 2017 |
| Cancellation of feedback digital-to-analog converter errors in multi-stage delta-sigma analog-to-digital converters JB Silva, J Zhao, WW Yang US Patent 9,231,614, 2016 | 8 | 2016 |
| Background static error measurement and timing skew error measurement for RF DAC J Zhao, H Shibata, G Engel US Patent 10,965,302, 2021 | 6 | 2021 |
| DAC calibration using VCO ADC J Zhao, ML Courcy, WW Yang, GE Taylor US Patent 10,727,853, 2020 | 5 | 2020 |
| Adaptive toggle number compensation for reducing data dependent supply noise in digital-to-analog converters H Luo, J Zhao, S Rose, D Li, L Zhang, T Wang US Patent 10,693,483, 2020 | 5 | 2020 |
| Multi-path dual-switch digital-to-analog converter H Luo, G Engel, S Rose, Y Chen, J Zhao US Patent 10,644,716, 2020 | 3 | 2020 |
| Background duty cycle error measurement for RF DAC J Zhao, H Shibata, G Engel, Y Dong US Patent 11,128,310, 2021 | 2 | 2021 |
| Background timing skew error measurement for RF DAC J Zhao, H Shibata, H Luo US Patent 11,075,643, 2021 | 1 | 2021 |
| Flash analog-to-digital converter calibration Z Li, H Shibata, TC Caldwell, Y Dong, J Zhao, RE Schreier, V Kozlov, ... US Patent 9,912,342, 2018 | 1 | 2018 |
