Yuxin Wang
Yuxin Wang
PhD student of Computer Science, Peking University
Verified email at pku.edu.cn
Cited by
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Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs
X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
Memory partitioning for multidimensional arrays in high-level synthesis
Y Wang, P Li, P Zhang, C Zhang, J Cong
Proceedings of the 50th Annual Design Automation Conference, 1-8, 2013
Theory and algorithm for generalized memory partitioning in high-level synthesis
Y Wang, P Li, J Cong
Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Y Wang, P Zhang, X Cheng, J Cong
17th Asia and South Pacific Design Automation Conference, 257-262, 2012
Memory partitioning and scheduling co-optimization in behavioral synthesis
P Li, Y Wang, P Zhang, G Luo, T Wang, J Cong
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 488-495, 2012
Source-to-source optimization for HLS
J Cong, M Huang, P Pan, Y Wang, P Zhang
FPGAs for Software Programmers, 137-163, 2016
Automatic multidimensional memory partitioning for FPGA-based accelerators
Y Wang, P Li, P Zhang, C Zhang, J Cong
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
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