| A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC A Elkholy, T Anand, WS Choi, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (4), 867-881, 2015 | 145 | 2015 |
| A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, 2016 | 90 | 2016 |
| Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers A Elkholy, M Talegaonkar, T Anand, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (12), 3160-3174, 2015 | 77 | 2015 |
| A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, 2015 | 77 | 2015 |
| A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 51 (8), 1771-1784, 2016 | 73 | 2016 |
| A 12-Gb/s-16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS MG Ahmed, M Talegaonkar, A Elkholy, G Shu, A Elmallah, A Rylyakov, ... IEEE Journal of Solid-State Circuits 53 (2), 445-457, 2018 | 56 | 2018 |
| 8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS D Coombs, A Elkholy, RK Nandwana, A Elmallah, PK Hanumolu 2017 IEEE International Solid-State Circuits Conference (ISSCC), 152-153, 2017 | 54 | 2017 |
| A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS J Zhu, RK Nandwana, G Shu, A Elkholy, SJ Kim, PK Hanumolu IEEE Journal of Solid-State Circuits 52 (1), 8-20, 2017 | 48 | 2017 |
| 19.8 A 0.0021 mm2 1.82 mW 2.2 GHz PLL using time-based integral control in 65nm CMOS J Zhu, RK Nandwana, G Shu, A Elkholy, SJ Kim, PK Hanumolu 2016 IEEE International Solid-State Circuits Conference (ISSCC), 338-340, 2016 | 48* | 2016 |
| A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, 2014 | 47* | 2014 |
| A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler A Elkholy, D Coombs, RK Nandwana, A Elmallah, PK Hanumolu IEEE Journal of Solid-State Circuits 54 (7), 2049-2058, 2019 | 44 | 2019 |
| Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers A Elkholy, S Saxena, G Shu, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (6), 1806-1817, 2018 | 40 | 2018 |
| A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS KM Megawer, A Elkholy, D Coombs, MG Ahmed, A Elmallah, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 392-394, 2018 | 36 | 2018 |
| 10.7 A 6.75-to-8.25GHz 2.25mW 190fsrmsintegrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in … A Elkholy, M Talegaonkar, T Anand, PK Hanumolu 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 36 | 2015 |
| A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier A Elkholy, A Elmallah, MG Ahmed, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (6), 1818-1829, 2018 | 33 | 2018 |
| 10.6 A 6.75-to-8.25 GHz, 250fsrms-integrated-jitter 3.25 mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS A Elkholy, A Elmallah, M Elzeftawi, K Chang, PK Hanumolu 2016 IEEE International Solid-State Circuits Conference (ISSCC), 192-193, 2016 | 33 | 2016 |
| Mixed-domain circuit with differential domain-converters A Elkholy US Patent 10,895,850, 2021 | 30 | 2021 |
| Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers KM Megawer, A Elkholy, MG Ahmed, A Elmallah, PK Hanumolu IEEE Journal of Solid-State Circuits 54 (1), 65-74, 2019 | 30 | 2019 |
| A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (12), 3101-3119, 2015 | 27 | 2015 |
| Fractional-N PLL-based CDR with a low-frequency reference G Shu, MN Elzeftawi, AM Elkholy US Patent 9,306,730, 2016 | 23 | 2016 |
Woo-Seok ChoiSeoul National University, Department of Electrical and Computer EngineeringVerified email at snu.ac.kr
