Proving optimizations correct using parameterized program equivalence S Kundu, Z Tatlock, S Lerner ACM Sigplan Notices 44 (6), 327-337, 2009 | 157 | 2009 |
Symbolic predictive analysis for concurrent programs C Wang, S Kundu, M Ganai, A Gupta International Symposium on Formal Methods, 256-272, 2009 | 111 | 2009 |
Validating high-level synthesis S Kundu, S Lerner, R Gupta Computer Aided Verification: 20th International Conference, CAV 2008 …, 2008 | 73 | 2008 |
Translation validation of high-level synthesis S Kundu, S Lerner, RK Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 64 | 2010 |
Partial order reduction for scalable testing of SystemC TLM designs S Kundu, M Ganai, R Gupta Proceedings of the 45th Annual Design Automation Conference, 936-941, 2008 | 56 | 2008 |
Automated refinement checking of concurrent systems S Kundu, S Lerner, R Gupta 2007 IEEE/ACM International Conference on Computer-Aided Design, 318-325, 2007 | 25 | 2007 |
Symbolic predictive analysis for concurrent programs C Wang, S Kundu, R Limaye, M Ganai, A Gupta Formal aspects of computing 23, 781-805, 2011 | 22 | 2011 |
Contessa: Concurrency Testing Augmented with Symbolic Analysis S Kundu, MK Ganai, C Wang Computer Aided Verification: 22nd International Conference, CAV 2010 …, 2010 | 19 | 2010 |
High-level Verification: Methods and Tools for Verification of System-level Designs S Kundu, S Lerner, R Gupta Springer Verlag, 2011 | 15* | 2011 |
Reduction of verification conditions for concurrent system using mutually atomic transactions MK Ganai, S Kundu International SPIN Workshop on Model Checking of Software, 68-87, 2009 | 9 | 2009 |
High-Level Verification S Kundu, S Lerner, R Gupta IPSJ Transactions on System and LSI Design Methodology 2, 131-144, 2009 | 6 | 2009 |
Translation Validation of High-Level Synthesis S Kundu, S Lerner, RK Gupta, S Kundu, S Lerner, RK Gupta High-Level Verification: Methods and Tools for Verification of System-Level …, 2011 | 3 | 2011 |
OaSis: an application specific operating system for an embedded environment GS Brar, S Kundu, P Worah, S Biswas, A Mukhopadhyay, A Basu 17th International Conference on VLSI Design. Proceedings., 776-779, 2004 | 3 | 2004 |
Parameterized Program Equivalence Checking S Kundu, S Lerner, RK Gupta, Z Tatlock High-Level Verification: Methods and Tools for Verification of System-Level …, 2011 | 1 | 2011 |
Bounded model checking for concurrent systems: Synchronous vs. asynchronous S Kundu, S Lerner, RK Gupta, MK Ganai High-Level Verification: Methods and Tools for Verification of System-Level …, 2011 | 1 | 2011 |
Formal Verification of Floating-Point Division A Kapoor, W Ferguson, H Jain, S Kundu 2023 IEEE 30th Symposium on Computer Arithmetic (ARITH), 93-96, 2023 | | 2023 |
High-level verification of system designs S Kundu University of California, San Diego, 2009 | | 2009 |