| A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ... IEEE International Solid-State Circuits Conference Digest of Technical …, 2010 | 844 | 2010 |
| A holistic analysis of circuit performance variations in 3-D ICs with thermal and TSV-induced stress considerations SK Marella, SS Sapatnekar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (7 …, 2014 | 24 | 2014 |
| Circuit reliability: from physics to architectures J Fang, S Gupta, SV Kumar, SK Marella, V Mishra, P Zhou, ... Proceedings of the International Conference on Computer-Aided Design, 243-246, 2012 | 20 | 2012 |
| A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations SK Marella, SV Kumar, SS Sapatnekar Proceedings of the International Conference on Computer-Aided Design, 317-324, 2012 | 18 | 2012 |
| The impact of shallow trench isolation effects on circuit performance SK Marella, SS Sapatnekar 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 289-294, 2013 | 14 | 2013 |
| Incorporating the role of stress on electromigration in power grids with via arrays V Mishra, P Jain, SK Marella, SS Sapatnekar Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 12 | 2017 |
| Optimization of FinFET-based circuits using a dual gate pitch technique SK Marella, AR Trivedi, S Mukhopadhyay, SS Sapatnekar Proceedings of the IEEE/ACM International Conference on Computer-Aided …, 2015 | 10 | 2015 |
| Circuit performance shifts due to layout-dependent stress in planar and 3D-ICs SSS SK Marella IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 3 | 2018 |
| Performance variations due to layout-dependent stress in VLSI circuits SK Marella University of Minnesota, 2015 | 2 | 2015 |
