| Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era S Ghosh, K Roy Proceedings of the IEEE 98 (10), 1718-1751, 2010 | 221 | 2010 |
| CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation S Ghosh, S Bhunia, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 145* | 2007 |
| Emerging trends in design and applications of memory-based computing and content-addressable memories R Karam, R Puri, S Ghosh, S Bhunia Proceedings of the IEEE 103 (8), 1311-1330, 2015 | 121 | 2015 |
| The Hardware Trojan War S Bhunia, M Tehranipoor Cham,, Switzerland: Springer, 2018 | 83 | 2018 |
| The Hardware Trojan War S Bhunia, M Tehranipoor Cham,, Switzerland: Springer, 2018 | 76 | 2018 |
| Low-power Variation-tolerant Design in Nanometer Silicon S Bhunia Springer Verlag, 2010 | 74 | 2010 |
| How secure are printed circuit boards against trojan attacks? S Ghosh, A Basak, S Bhunia IEEE Design & Test 32 (2), 7-16, 2014 | 70 | 2014 |
| Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking S Ghosh, D Mohapatra, G Karakonstantis, K Roy IEEE transactions on very large scale integration (VLSI) systems 18 (9 …, 2009 | 68 | 2009 |
| 13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology F Hamzaoglu, U Arslan, N Bisnik, S Ghosh, MB Lal, N Lindert, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 62 | 2014 |
| QURE: Qubit re-allocation in noisy intermediate-scale quantum computers A Ash-Saki, M Alam, S Ghosh Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 58 | 2019 |
| Impact of process-variations in STTRAM and adaptive boosting for robustness S Motaman, S Ghosh, N Rathi 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 51 | 2015 |
| A novel on-chip delay measurement hardware for efficient speed-binning A Raychowdhury, S Ghosh, K Roy 11th IEEE International On-Line Testing Symposium, 287-292, 2005 | 49 | 2005 |
| Spintronics and security: Prospects, vulnerabilities, attack models, and preventions S Ghosh Proceedings of the IEEE 104 (10), 1864-1893, 2016 | 47 | 2016 |
| A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking S Ghosh, P Ndai, K Roy Proceedings of the conference on Design, automation and test in Europe, 366-371, 2008 | 47 | 2008 |
| A novel delay fault testing methodology using low-overhead built-in delay sensor S Ghosh, S Bhunia, A Raychowdhury, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 47 | 2006 |
| Self-correcting STTRAM under magnetic field attacks JW Jang, J Park, S Ghosh, S Bhunia 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015 | 46 | 2015 |
| A novel threshold voltage defined switch for circuit camouflaging IR Nirmala, D Vontela, S Ghosh, A Iyengar 2016 21th IEEE European Test Symposium (ETS), 1-2, 2016 | 41 | 2016 |
| Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6 V 32nm LP SRAM Y Wang, E Karl, M Meterelliyoz, F Hamzaoglu, YG Ng, S Ghosh, L Wei, ... 2011 International Electron Devices Meeting, 32.1. 1-32.1. 4, 2011 | 41 | 2011 |
| MUQUT: Multi-constraint quantum circuit mapping on NISQ computers D Bhattacharjee, AA Saki, M Alam, A Chattopadhyay, S Ghosh 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2019 | 38* | 2019 |
| DWM-PUF: A low-overhead, memory-based security primitive A Iyengar, K Ramclam, S Ghosh 2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014 | 38 | 2014 |
Kaushik RoyProfessor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
