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Erik Larsson
Erik Larsson
Verified email at eit.lth.se - Homepage
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Cited by
Year
An integrated framework for the design and optimization of SOC test solutions
E Larsson, Z Peng, K Chakrabarty
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 21-36, 2002
1122002
An integrated system-on-chip test framework
E Larsson, Z Peng
Design, Automation, and Test in Europe, 439-454, 2008
1112008
Efficient test solutions for core-based designs
E Larsson
Introduction to Advanced System-on-Chip Test Design and Optimization, 215-251, 2005
752005
Design automation for IEEE P1687
FG Zadegan, U Ingelsson, G Carlsson, E Larsson
2011 Design, Automation & Test in Europe, 1-6, 2011
672011
Test scheduling and scan-chain division under power constraint
E Larsson, Z Peng
Proceedings 10th Asian Test Symposium, 259-264, 2001
672001
Cycle-accurate test power modeling and its application to SoC test scheduling
S Samii, E Larsson, K Chakrabarty, Z Peng
2006 IEEE International Test Conference, 1-10, 2006
482006
System-on-chip test scheduling with reconfigurable core wrappers
E Larsson, H Fujiwara
IEEE transactions on very large scale integration (VLSI) systems 14 (3), 305-309, 2006
482006
Introduction to advanced system-on-chip test design and optimization
E Larsson
Springer Science & Business Media, 2005
482005
A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling.
E Larsson, Z Peng
ITC, 1135-1144, 2003
472003
Access time analysis for IEEE P1687
FG Zadegan, U Ingelsson, G Carlsson, E Larsson
IEEE Transactions on Computers 61 (10), 1459-1472, 2011
422011
Multiple-constraint driven system-on-chip test time optimization
J Pouget, E Larsson, Z Peng
Journal of electronic testing 21 (6), 599-611, 2005
422005
Test scheduling for modular SOCs in an abort-on-fail environment
U Ingelsson, SK Goel, E Larsson, EJ Marinissen
European Test Symposium (ETS'05), 8-13, 2005
422005
A suite of IEEE 1687 benchmark networks
A Tšertov, A Jutman, S Devadze, MS Reorda, E Larsson, FG Zadegan, ...
2016 IEEE International Test Conference (ITC), 1-10, 2016
402016
On minimization of peak power for scan circuit during test
JT Tudu, E Larsson, V Singh, VD Agrawal
2009 14th IEEE European Test Symposium, 25-30, 2009
382009
Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns
A Larsson, E Larsson, K Chakrabarty, P Eles, Z Peng
2008 Design, Automation and Test in Europe, 188-193, 2008
382008
SOC test time minimization under multiple constraints
J Pouget, E Larsson, Z Peng
2003 Test Symposium, 312-312, 2003
382003
Power constrained preemptive TAM scheduling
E Larsson, H Fujiwara
Proceedings The Seventh IEEE European Test Workshop, 119-126, 2002
372002
Defect-aware SOC test scheduling
E Larsson, J Pouget, Z Peng
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 359-364, 2004
362004
Cycle-accurate test power modeling and its application to SoC test architecture design and scheduling
S Samii, M Selkala, E Larsson, K Chakrabarty, Z Peng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
352008
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
P Subramanyan, V Singh, KK Saluja, E Larsson
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
342010
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