Isask'har Walter
Isask'har Walter
Unknown affiliation
Verified email at tx.technion.ac.il
Title
Cited by
Cited by
Year
Efficient link capacity and QoS design for network-on-chip
Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
852006
Network delays and link capacities in application-specific wormhole NoCs
Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny
VLSI design 2007, 2007
632007
Best of both worlds: A bus enhanced NoC (BENoC)
R Manevich, I Cidon, A Kolodny
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 173-182, 2009
442009
Access regulation to hot-modules in wormhole NoCs
I Cidon, R Ginosar, A Kolodny
First International Symposium on Networks-on-Chip (NOCS'07), 137-148, 2007
442007
A cost effective centralized adaptive routing for networks-on-chip
R Manevich, I Cidon, A Kolodny, S Wimer
2011 14th Euromicro Conference on Digital System Design, 39-46, 2011
362011
Centralized adaptive routing for NoCs
R Manevich, I Cidon
IEEE Computer Architecture Letters 9 (2), 57-60, 2010
242010
Benoc: A bus-enhanced network on-chip for a power efficient CMP
I Cidon, A Kolodny
IEEE Computer Architecture Letters 7 (2), 61-64, 2008
202008
The era of many-modules SoC: revisiting the NoC mapping problem
I Walter, I Cidon, A Kolodny, D Sigalov
Proceedings of the 2nd International Workshop on Network on Chip …, 2009
172009
Leveraging application-level requirements in the design of a NoC for a 4G SoC-a case study
R Beraha, I Cidon, A Kolodny
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
142010
Static timing analysis for modeling QoS in networks-on-chip
E Krimer, I Keslassy, A Kolodny, M Erez
Journal of Parallel and Distributed Computing 71 (5), 687-699, 2011
92011
Packet-level static timing analysis for NoCs
E Krimer, M Erez, I Keslassy, A Kolodny
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 88-88, 2009
52009
Capacity optimized NoC for multi-mode SoC
I Walter, E Kantor, I Cidon, S Kutten
Proceedings of the 48th Design Automation Conference, 942-947, 2011
42011
Curing Hotspots in Wormhole NoCs
AC Isask’har Walter, R Ginosar, A Kolodny
DATE, ElectricalEngineering Department, 2006
32006
The design of a latency constrained, power optimized NoC for a 4G SoC
R Beraha, I Cidon, A Kolodny
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 86-86, 2009
22009
SpaceWire Hot Modules
A Baron, IC Isask'har Walter, R Ginosar, I Keslassy, O Lapid
Int. SpaceWire Conf, 2007
12007
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip
A Kolodny, I Walter, S Wimer, I Cidon, R Manevich
2011
Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study
R Beraha, I Cidon, A Kolodny
Low Power Networks-on-Chip, 175-195, 2011
2011
The Design of a Latency Constrained, Power Optimized NoC for a 4G SoC
IC Isask’har Walter, A Kolodny, R Beraha
2009
BENoC: A bus-Enhanced Network on-Chip
IC Isask'har Walter, A Kolodny
2007
CCIT REPORT# 724 March 2009
IC Isask'har Walter, A Kolodny, R Beraha
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