| Semiconductor device and manufacturing method thereof K Mori, D Ohshima, S Yamamichi, H Murai, K Maeda, K Kikuchi, ... US Patent 8,569,892, 2013 | 86 | 2013 |
| Wiring board capable of containing functional element and method for manufacturing same T Funaya, S Yamamichi, D Ohshima, Y Nakashima US Patent 8,692,135, 2014 | 85 | 2014 |
| Semiconductor element-embedded substrate, and method of manufacturing the substrate K Mori, S Yamamichi, H Murai, K Kikuchi, Y Nakashima, D Ohshima US Patent 8,810,008, 2014 | 62 | 2014 |
| Wiring board with built-in semiconductor element K Kikuchi, S Yamamichi, H Murai, K Mori, Y Nakashima, D Ohshima US Patent 8,766,440, 2014 | 38 | 2014 |
| Semiconductor device built-in substrate K Mori, S Yamamichi, K Kikuchi, D Ohshima, Y Nakashima, H Murai US Patent App. 13/638,421, 2013 | 22 | 2013 |
| Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer K Mori, Y Nakashima, D Ohshima, K Kikuchi, S Yamamichi US Patent 8,710,669, 2014 | 17 | 2014 |
| Semiconductor device and method for designing the same H Sasaki, D Ohshima, T Funaya US Patent 8,450,843, 2013 | 14 | 2013 |
| Electrical design and demonstration of an embedded high-pin-count LSI chip package D Ohshima, H Sasaki, K Mori, Y Fujimura, K Kikuchi, Y Nakashima, ... 2009 59th Electronic Components and Technology Conference, 482-488, 2009 | 13 | 2009 |
| A novel ultra-thin package for embedded high-pin-count LSI supported by Cu plate K Mori, D Ohshima, H Sasaki, Y Fujimura, K Kikuchi, Y Nakashima, ... 2009 59th Electronic Components and Technology Conference, 1447-1452, 2009 | 11 | 2009 |
| Substrate with built-in functional element D Ohshima, K Mori, Y Nakashima, K Kikuchi, S Yamamichi US Patent App. 13/639,486, 2013 | 8 | 2013 |
| Functional device-embedded substrate D Ohshima, K Kikuchi, Y Nakashima, K Mori, S Yamamichi US Patent App. 13/634,088, 2013 | 6 | 2013 |
| Silicon-photonics-embedded interposers as co-packaged optics platform K Takemura, D Ohshima, A Noriki, D Okamoto, A Ukita, J Ushida, ... Transactions of The Japan Institute of Electronics Packaging 15, E21-012-1 …, 2022 | 5 | 2022 |
| Silicon-photonics-embedded interposers and their applications K Takemura, D Ohshima, A Noriki, D Okamoto, A Ukita, J Ushida, ... 2021 International Conference on Electronics Packaging (ICEP), 35-36, 2021 | 4 | 2021 |
| Embedded Active Packaging Technology for High-Pin-Count LSI With Cu Plate K Mori, D Ohshima, H Sasaki, Y Fujimura, K Kikuchi, Y Nakashima, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (1 …, 2010 | 4 | 2010 |
| Reliability of thin seamless package with embedded high-pin-count LSI chip K Mori, K Kikuchi, D Ohshima, Y Nakashima, S Yamamichi 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC …, 2010 | 4 | 2010 |
| Chip-level and package-level seamless interconnect technologies for advanced packaging S Yamamichi, K Mori, K Kikuchi, H Murai, D Ohshima, Y Nakashima, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 3 | 2009 |
| Information processing device, information processing system, information processing method and computer-readable medium Y Motohashi, H Sakagami, S Kamei, D Ohshima US Patent 9,886,666, 2018 | 2 | 2018 |
| Semiconductor device and manufacturing method thereof K Mori, D Ohshima, S Yamamichi, H Murai, K Maeda, K Kikuchi, ... US Patent App. 14/033,855, 2014 | 2 | 2014 |
| Warpage Mechanism of Thin Embedded LSI Packages Y Nakashima, K Kikuchi, K Mori, D Ohshima, S Yamamichi Transactions of The Japan Institute of Electronics Packaging 3 (1), 47-56, 2010 | 2 | 2010 |
| Analysis method and analysis apparatus of designing transmission lines of an integrated circuit packaging board H Inoue, D Ohshima, J Sakai, M Furuya US Patent 7,434,190, 2008 | 2 | 2008 |
