| Backfilling using system-generated predictions rather than user runtime estimates D Tsafrir, Y Etsion, DG Feitelson IEEE Transactions on Parallel and Distributed Systems 18 (6), 789-803, 2007 | 575 | 2007 |
| System noise, OS clock ticks, and fine-grained parallel applications D Tsafrir, Y Etsion, DG Feitelson, S Kirkpatrick Proceedings of the 19th annual international conference on Supercomputing …, 2005 | 211 | 2005 |
| Task superscalar: An out-of-order task pipeline Y Etsion, F Cabarcas, A Rico, A Ramirez, RM Badia, E Ayguade, ... 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 89-100, 2010 | 184* | 2010 |
| Modeling user runtime estimates D Tsafrir, Y Etsion, DG Feitelson Job Scheduling Strategies for Parallel Processing: 11th International …, 2005 | 169 | 2005 |
| Didi: Mitigating the performance impact of tlb shootdowns using a shared tlb directory C Villavieja, V Karakostas, L Vilanova, Y Etsion, A Ramirez, A Mendelson, ... 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 155 | 2011 |
| A short survey of commercial cluster batch schedulers Y Etsion, D Tsafrir School of Computer Science and Engineering, The Hebrew University of …, 2005 | 135 | 2005 |
| Semantic locality and context-based prefetching using reinforcement learning L Peled, S Mannor, U Weiser, Y Etsion Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 130 | 2015 |
| Trace-driven simulation of multithreaded applications A Rico, A Duran, F Cabarcas, Y Etsion, A Ramirez, M Valero (IEEE ISPASS) IEEE International Symposium on Performance Analysis of …, 2011 | 106 | 2011 |
| CODOMs: Protecting software with code-centric memory domains L Vilanova, M Ben-Yehuda, N Navarro, Y Etsion, M Valero ACM SIGARCH Computer Architecture News 42 (3), 469-480, 2014 | 101 | 2014 |
| Hybrid dataflow/von-Neumann architectures F Yazdanpanah, C Alvarez-Martinez, D Jimenez-Gonzalez, Y Etsion IEEE Transactions on Parallel and Distributed Systems 25 (6), 1489-1509, 2013 | 100 | 2013 |
| Single-graph multiple flows: Energy efficient design alternative for gpgpus D Voitsechov, Y Etsion ACM SIGARCH computer architecture news 42 (3), 205-216, 2014 | 93 | 2014 |
| Do-it-yourself virtual memory translation H Alam, T Zhang, M Erez, Y Etsion ACM SIGARCH Computer Architecture News 45 (2), 457-468, 2017 | 81 | 2017 |
| A neural network prefetcher for arbitrary memory access patterns L Peled, U Weiser, Y Etsion ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-27, 2019 | 77* | 2019 |
| Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware Y Etsion, D Voitsechov US Patent App. 14/642,780, 2015 | 73 | 2015 |
| Effects of clock resolution on the scheduling of interactive and soft real-time processes Y Etsion, D Tsafrir, DG Feitelson Proceedings of the 2003 ACM SIGMETRICS international conference on …, 2003 | 69* | 2003 |
| Secretly Monopolizing the CPU Without Superuser Privileges. D Tsafrir, Y Etsion, DG Feitelson USENIX Security Symposium, 239-256, 2007 | 64 | 2007 |
| Flexible caching in trie joins O Kalinsky, Y Etsion, B Kimelfeld arXiv preprint arXiv:1602.08721, 2016 | 60 | 2016 |
| L1 cache filtering through random selection of memory references Y Etsion, DG Feitelson 16th International Conference on Parallel Architecture and Compilation …, 2007 | 53* | 2007 |
| Process prioritization using output production: scheduling for multimedia Y Etsion, D Tsafrir, DG Feitelson ACM Transactions on Multimedia Computing, Communications, and Applications …, 2006 | 52* | 2006 |
| On the simulation of large-scale architectures using multiple application abstraction levels A Rico Carro, F Cabarcas, C Villavieja Prados, M Pavlovic, A Vega, ... ACM transactions on architecture and code optimization 8 (4), 36: 1-36: 20, 2012 | 49 | 2012 |
Dror FeitelsonHebrew UniversityVerified email at cs.huji.ac.il
