| DAG-aware AIG rewriting: A fresh look at combinational logic synthesis A Mishchenko, S Chatterjee, R Brayton 2006 43rd ACM/IEEE Design Automation Conference, 532-535, 2006 | 507 | 2006 |
| Improvements to technology mapping for LUT-based FPGAs A Mishchenko, S Chatterjee, R Brayton Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field …, 2006 | 197 | 2006 |
| Improvements to combinational equivalence checking A Mishchenko, S Chatterjee, R Brayton, N Een 2006 IEEE/ACM International Conference on Computer Aided Design, 836-843, 2006 | 178 | 2006 |
| Combinational and sequential mapping with priority cuts A Mishchenko, S Cho, S Chatterjee, R Brayton 2007 IEEE/ACM International Conference on Computer-Aided Design, 354-361, 2007 | 177 | 2007 |
| Reducing structural bias in technology mapping S Chatterjee, A Mishchenko, RK Brayton, X Wang, T Kam IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 158 | 2006 |
| FRAIGs: A unifying representation for logic synthesis and verification A Mishchenko, S Chatterjee, R Jiang, RK Brayton ERL Technical Report, 2005 | 154 | 2005 |
| Verifying deadlock-freedom of communication fabrics A Gotmanov, S Chatterjee, M Kishinevsky International Workshop on Verification, Model Checking, and Abstract …, 2011 | 57 | 2011 |
| xMAS: Quick formal modeling of communication fabrics to enable verification S Chatterjee, M Kishinevsky, UY Ogras IEEE Design & Test of Computers 29 (3), 80-88, 2012 | 56 | 2012 |
| Boolean factoring and decomposition of logic networks A Mishchenko, R Brayton, S Chatterjee 2008 IEEE/ACM International Conference on Computer-Aided Design, 38-44, 2008 | 51 | 2008 |
| Factor cuts S Chatterjee, A Mishchenko, R Brayton Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 49 | 2006 |
| Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics S Chatterjee, M Kishinevsky International Conference on Computer Aided Verification, 321-338, 2010 | 48 | 2010 |
| Quick formal modeling of communication fabrics to enable verification S Chatterjee, M Kishinevsky, UY Ogras 2010 IEEE International High Level Design Validation and Test Workshop …, 2010 | 45 | 2010 |
| Integrating logic synthesis, technology mapping, and retiming A Mishchenko, S Chatterjee, R Brayton Proc. IWLS'05, 2006 | 32 | 2006 |
| Learning and memorization S Chatterjee International Conference on Machine Learning, 755-763, 2018 | 30 | 2018 |
| Technology mapping with Boolean matching, supergates and choices A Mishchenko, S Chatterjee, R Brayton, X Wang, T Kam | 28 | 2005 |
| An integrated technology mapping environment R Brayton, S Chatterjee, M Ciesielski, A Mishchenko Proc. International Workshop on Logic and Synthesis, 383-390, 2005 | 25 | 2005 |
| Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics S Chatterjee, M Kishinevsky Formal Methods in System Design 40 (2), 147-169, 2012 | 24 | 2012 |
| Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics S Chatterjee, M Kishinevsky Formal Methods in System Design 40 (2), 147-169, 2012 | 24 | 2012 |
| Coherent gradients: An approach to understanding generalization in gradient descent-based optimization S Chatterjee arXiv preprint arXiv:2002.10657, 2020 | 23 | 2020 |
| On resolution proofs for combinational equivalence S Chatterjee, A Mishchenko, R Brayton, A Kuehlmann Proceedings of the 44th annual Design Automation Conference, 600-605, 2007 | 19 | 2007 |
Umit Y. OgrasUniversity of Wisconsin-MadisonVerified email at wisc.edu
