Yaojun Zhang
Yaojun Zhang
Ph.D. Student of Electrical Engineering, University of Pittsburgh
Verified email at pitt.edu
Title
Cited by
Cited by
Year
Asymmetry of MTJ switching and its implication to STT-RAM designs
Y Zhang, X Wang, Y Li, AK Jones, Y Chen
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
972012
Multi-level cell STT-RAM: Is it realistic or just a dream?
Y Zhang, L Zhang, W Wen, G Sun, Y Chen
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 526-532, 2012
962012
STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view
Y Zhang, X Wang, Y Chen
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 471-477, 2011
892011
Exploration of GPGPU register file architecture using domain-wall-shift-write based racetrack memory
M Mao, W Wen, Y Zhang, Y Chen, H Li
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
812014
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
Y Chen, WF Wong, H Li, CK Koh, Y Zhang, W Wen
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (2), 1-22, 2013
582013
A compact modeling of TiO2-TiO2–x memristor
L Zhang, Z Chen, J Joshua Yang, B Wysocki, N McDonald, Y Chen
Applied Physics Letters 102 (15), 153503, 2013
542013
The prospect of STT-RAM scaling from readability perspective
Y Zhang, W Wen, Y Chen
IEEE Transactions on Magnetics 48 (11), 3035-3038, 2012
472012
STT-RAM cell optimization considering MTJ and CMOS variations
Y Zhang, X Wang, H Li, Y Chen
IEEE transactions on magnetics 47 (10), 2962-2965, 2011
472011
Read performance: The newest barrier in scaled STT-RAM
Y Zhang, Y Li, Z Sun, H Li, Y Chen, AK Jones
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (6 …, 2014
442014
Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement
H Li, X Wang, ZL Ong, WF Wong, Y Zhang, P Wang, Y Chen
IEEE Transactions on Magnetics 47 (10), 2356-2359, 2011
432011
State-restrict MLC STT-RAM designs for high-reliable high-performance memory system
W Wen, Y Zhang, M Mao, Y Chen
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
422014
PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method
W Wen, Y Zhang, Y Chen, Y Wang, Y Xie
DAC Design Automation Conference 2012, 1187-1192, 2012
392012
Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach
J Yang, P Wang, Y Zhang, Y Cheng, W Zhao, Y Chen, HH Li
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
322015
Improving energy efficiency of write-asymmetric memories by log style write
G Sun, Y Zhang, Y Wang, Y Chen
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
302012
Electrode-material dependent switching in TaO x memristors
N Ge, MX Zhang, L Zhang, JJ Yang, Z Li, RS Williams
Semiconductor Science and Technology 29 (10), 104003, 2014
272014
ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications
Y Zhang, I Bayram, Y Wang, H Li, Y Chen
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 9-16, 2013
272013
Giant spin hall effect (GSHE) logic design for low power application
Y Zhang, B Yan, W Wu, H Li, Y Chen
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
242015
A novel self-reference technique for STT-RAM read and write reliability enhancement
E Eken, Y Zhang, W Wen, R Joshi, H Li, Y Chen
IEEE Transactions on Magnetics 50 (11), 1-4, 2014
232014
C1C: A configurable, compiler-guided STT-RAM L1 cache
Y Li, Y Zhang, H Li, Y Chen, AK Jones
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-22, 2013
222013
Low voltage two-state-variable memristor model of vacancy-drift resistive switches
L Zhang, N Ge, JJ Yang, Z Li, RS Williams, Y Chen
Applied Physics A 119 (1), 1-9, 2015
202015
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Articles 1–20