Radu Teodorescu
Title
Cited by
Cited by
Year
VARIUS: A model of process variation and resulting timing errors for microarchitects
SR Sarangi, B Greskamp, R Teodorescu, J Nakano, A Tiwari, J Torrellas
IEEE Transactions on Semiconductor Manufacturing 21 (1), 3-13, 2008
4542008
Variation-aware application scheduling and power management for chip multiprocessors
R Teodorescu, J Torrellas
ACM SIGARCH computer architecture news 36 (3), 363-374, 2008
3742008
HARD: Hardware-assisted lockset-based race detection
P Zhou, R Teodorescu, Y Zhou
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
1722007
Caching with selective multicasting in a publish-subscribe network
S Yajnik, TW Chen, PF Yang, R Teodorescu
US Patent 7,672,275, 2010
1532010
Mitigating parameter variation with dynamic fine-grain body biasing
R Teodorescu, J Nakano, A Tiwari, J Torrellas
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
1292007
One bit flips, one cloud flops: Cross-vm row hammer attacks and privilege escalation
Y Xiao, X Zhang, Y Zhang, R Teodorescu
25th {USENIX} Security Symposium ({USENIX} Security 16), 19-35, 2016
1172016
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips
TN Miller, X Pan, R Thomas, N Sedaghati, R Teodorescu
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
882012
Log-based architectures for general-purpose monitoring of deployed code
S Chen, B Falsafi, PB Gibbons, M Kozuch, TC Mowry, R Teodorescu, ...
Proceedings of the 1st workshop on Architectural and system support for …, 2006
802006
Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors
A Bacha, R Teodorescu
Proceedings of the 40th Annual International Symposium on Computer …, 2013
692013
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
TN Miller, R Thomas, X Pan, R Teodorescu
ACM SIGARCH Computer Architecture News 40 (3), 249-260, 2012
572012
Parichute: Generalized turbocode-based error correction for near-threshold caches
TN Miller, R Thomas, J Dinan, B Adcock, R Teodorescu
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 351-362, 2010
512010
Using ECC feedback to guide voltage speculation in low-voltage processors
A Bacha, R Teodorescu
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 306-318, 2014
452014
Packet routing via payload inspection for digital content delivery
TW Chen, PF Yang, R Leng, CY Wang, R Teodorescu, Y Huang, ...
US Patent App. 10/613,994, 2004
332004
SWICH: A prototype for efficient cache-level checkpointing and rollback
R Teodorescu, J Nakano, J Torrellas
IEEE Micro 26 (5), 28-40, 2006
322006
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Stages
TN Miller, R Thomas, R Teodorescu
Workshop on Energy-Efficient Design (WEED), in conjunction with ISCA, 2011
302011
Authenticache: Harnessing cache ECC for system authentication
A Bacha, R Teodorescu
Proceedings of the 48th International Symposium on Microarchitecture, 128-140, 2015
242015
EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures
R Thomas, N Sedaghati, R Teodorescu
2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016
182016
Core tunneling: Variation-aware voltage noise mitigation in gpus
R Thomas, K Barber, N Sedaghati, L Zhou, R Teodorescu
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
182016
NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores
X Pan, R Teodorescu
2014 IEEE 32nd International Conference on Computer Design (ICCD), 400-407, 2014
172014
StVEC: A Vector Instruction Extension for High Performance Stencil Computation
N Sedaghati, R Thomas, LN Pouchet, R Teodorescu, P Sadayappan
International Conference on Parallel Architectures and Compilation …, 2011
172011
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Articles 1–20