Chuck Alpert
Chuck Alpert
Senior Software Architect, Cadence Design Systems
Verified email at cadence.com
Title
Cited by
Cited by
Year
Recent directions in netlist partitioning: a survey
CJ Alpert, AB Kahng
Integration 19 (1-2), 1-81, 1995
8821995
The ISPD98 circuit benchmark suite
CJ Alpert
Proceedings of the 1998 international symposium on Physical design, 80-85, 1998
3791998
Multilevel circuit partitioning
CJ Alpert, JH Huang, AB Kahng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
3661998
A clock distribution network for microprocessors
PJ Restle, TG McNamara, DA Webber, PJ Camporese, KF Eng, ...
IEEE Journal of Solid-State Circuits 36 (5), 792-799, 2001
3532001
Buffer insertion for noise and delay optimization
CJ Alpert, A Devgan, ST Quay
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
2641999
Wire segmenting for improved buffer insertion
C Alpert, A Devgan
Proceedings of the 34th annual Design Automation Conference, 588-593, 1997
2551997
Spectral partitioning: the more eigenvectors, the better
CJ Alpert, SZ Yao
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 195-200, 1995
2401995
Handbook of algorithms for physical design automation
CJ Alpert, DP Mehta, SS Sapatnekar
CRC press, 2008
2372008
Spectral partitioning with multiple eigenvectors
CJ Alpert, AB Kahng, SZ Yao
Discrete Applied Mathematics 90 (1-3), 3-26, 1999
2161999
A practical methodology for early buffer and wire resource allocation
CJ Alpert, J Hu, SS Sapatnekar, PG Villarrubia
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
1752003
RC delay metrics for performance optimization
CJ Alpert, A Devgan, CV Kashyap
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
1622001
The ISPD2005 placement contest and benchmark suite
GJ Nam, CJ Alpert, P Villarrubia, B Winter, M Yildiz
Proceedings of the 2005 international symposium on Physical design, 216-220, 2005
1442005
Buffer insertion with accurate gate and interconnect delay computation
CJ Alpert, A Devgan, ST Quay
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 479-484, 1999
1391999
Porosity aware buffered steiner tree construction
CJ Alpert, RG Gandham, J Hu, ST Quay
US Patent 7,065,730, 2006
1332006
A practical methodology for early buffer and wire resource allocation
CJ Alpert, J Hu, SS Sapatnekar, PG Villarrubia
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
1112003
The ISPD-2011 routability-driven placement contest and benchmark suite
N Viswanathan, CJ Alpert, C Sze, Z Li, GJ Nam, JA Roy
Proceedings of the 2011 international symposium on Physical design, 141-146, 2011
972011
A hybrid multilevel/genetic approach for circuit partitioning
CJ Alpert, LW Hagen, AB Kahng
Proceedings of APCCAS'96-Asia Pacific Conference on Circuits and Systems …, 1996
971996
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
CJ Alpert, TC Hu, JH Huang, AB Kahng, D Karger
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
971995
Faster minimization of linear wirelength for global placement
CJ Alpert, TF Chan, AB Kahng, IL Markov, P Mulet
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
951998
Method and system for re-routing interconnects within an integrated circuit design having blockages and bays
CJ Alpert, RG Gandham, J Hu, JL Neves, ST Quay
US Patent 6,401,234, 2002
942002
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