Ruchir Puri
Ruchir Puri
Chief Scientist, IBM Research; IBM Fellow
Verified email at - Homepage
Cited by
Cited by
Turning silicon on its edge [double gate CMOS/FinFET technology]
EJ Nowak, I Aller, T Ludwig, K Kim, RV Joshi, CT Chuang, K Bernstein, ...
IEEE Circuits and Devices Magazine 20 (1), 20-31, 2004
Interconnects in the third dimension: Design challenges for 3D ICs
K Bernstein, P Andry, J Cann, P Emma, D Greenberg, W Haensch, ...
Proceedings of the 44th annual Design Automation Conference, 562-567, 2007
Explainable machine learning in deployment
U Bhatt, A Xiang, S Sharma, A Weller, A Taly, Y Jia, J Ghosh, R Puri, ...
Proceedings of the 2020 conference on fairness, accountability, and …, 2020
Handbook of algorithms for physical design automation
CJ Alpert, DP Mehta, SS Sapatnekar
CRC press, 2008
Pushing ASIC performance in a power envelope
R Puri, L Stok, J Cohn, D Kung, D Pan, D Sylvester, A Srivastava, ...
Proceedings of the 40th annual Design Automation Conference, 788-793, 2003
Emerging trends in design and applications of memory-based computing and content-addressable memories
R Karam, R Puri, S Ghosh, S Bhunia
Proceedings of the IEEE 103 (8), 1311-1330, 2015
Design and CAD challenges in sub-90nm CMOS technologies
K Bernstein, CT Chuang, R Joshi, R Puri
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
The next generation of deep learning hardware: Analog computing
W Haensch, T Gokmen, R Puri
Proceedings of the IEEE 107 (1), 108-122, 2018
Three-dimensional architecture for self-checking and self-repairing integrated circuits
K Bernstein, PW Coteus, IAM Elfadel, PG Emma, KW Guarini, ...
US Patent App. 11/621,188, 2008
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
EJ Fluhr, J Friedrich, D Dreps, V Zyuban, G Still, C Gonzalez, A Hall, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
Wire density driven global routing for CMP variation and timing
M Cho, DZ Pan, H Xiang, R Puri
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
An integrated environment for technology closure of deep-submicron IC designs
L Trevillyan, D Kung, R Puri, LN Reddy, MA Kazda
IEEE Design & Test of Computers 21 (1), 14-22, 2004
Relative ordering circuit synthesis
M Cho, R Puri, H Ren, X Tang, H Xiang, MM Ziegler
US Patent 8,756,541, 2014
Logic optimization by output phase assignment in dynamic logic synthesis
R Puri, A Bjorksten, TE Rosser
Proceedings of International Conference on Computer Aided Design, 2-8, 1996
Bias mitigation post-processing for individual and group fairness
PK Lohia, KN Ramamurthy, M Bhide, D Saha, KR Varshney, R Puri
Icassp 2019-2019 ieee international conference on acoustics, speech and …, 2019
Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits
R Puri, J Gu
US Patent 5,469,367, 1995
Closing the power gap between ASIC & custom: tools and techniques for low power design
D Chinnery, K Keutzer
Springer Science & Business Media, 2008
CodeNet: A large-scale AI for code dataset for learning a diversity of coding tasks
R Puri, DS Kung, G Janssen, W Zhang, G Domeniconi, V Zolotov, J Dolby, ...
arXiv preprint arXiv:2105.12655, 2021
DeltaSyn: An efficient logic difference optimizer for ECO synthesis
S Krishnaswamy, H Ren, N Modi, R Puri
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
Asynchronous circuit synthesis with boolean satisfiability
J Gu, R Puri
IEEE transactions on computer-aided design of integrated circuits and …, 1995
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