Siavash Bayat Sarmadi
Title
Cited by
Cited by
Year
On concurrent detection of errors in polynomial basis multiplication
S Bayat-Sarmadi, MA Hasan
IEEE transactions on very large scale integration (vlsi) systems 15 (4), 413-426, 2007
652007
Efficient and concurrent reliable realization of the secure cryptographic SHA-3 algorithm
S Bayat-Sarmadi, M Mozaffari-Kermani, A Reyhani-Masoleh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
572014
Concurrent error detection in finite-field arithmetic operations using pipelined and systolic architectures
S Bayat-Sarmadi, MA Hasan
IEEE Transactions on computers 58 (11), 1553-1567, 2009
462009
A hybrid fault injection approach based on simulation and emulation co-operation
A Ejlali, SG Miremadi, H Zarandi, G Asadi, SB Sarmadi
2003 International Conference on Dependable Systems and Networks, 2003 …, 2003
422003
On constrained implementation of lattice-based cryptographic primitives and schemes on smart cards
A Boorghany, SB Sarmadi, R Jalili
ACM Transactions on Embedded Computing Systems (TECS) 14 (3), 1-25, 2015
412015
Fault-resilient lightweight cryptographic block ciphers for secure embedded systems
M Mozaffari-Kermani, K Tian, R Azarderakhsh, S Bayat-Sarmadi
IEEE Embedded Systems Letters 6 (4), 89-92, 2014
382014
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over
M Mozaffari-Kermani, R Azarderakhsh, CY Lee, S Bayat-Sarmadi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5), 995 …, 2013
372013
Fpga-based protection scheme against hardware trojan horse insertion using dummy logic
B Khaleghi, A Ahari, H Asadi, S Bayat-Sarmadi
IEEE Embedded Systems Letters 7 (2), 46-50, 2015
312015
Systolic Gaussian normal basis multiplier architectures suitable for high-performance applications
R Azarderakhsh, MM Kermani, S Bayat-Sarmadi, CY Lee
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (9 …, 2014
202014
Dual-basis superserial multipliers for secure applications and lightweight cryptographic architectures
S Bayat-Sarmadi, MM Kermani, R Azarderakhsh, CY Lee
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (2), 125-129, 2013
182013
Concurrent error detection of polynomial basis multiplication over extension fields using a multiple-bit parity scheme
S Bayat-Sarmadi, MA Hasan
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005
182005
High-Throughput Low-Complexity Systolic Montgomery Multiplication OverBased on Trinomials
S Bayat-Sarmadi, M Farmani
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (4), 377-381, 2015
122015
A low-latency and low-complexity point-multiplication in ECC
R Salarifard, S Bayat-Sarmadi, H Mosanaei-Boorani
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 2869-2877, 2018
112018
Run-time error detection in polynomial basis multiplication using linear codes
S Bayat-Saramdi, MA Hasan
2007 IEEE International Conf. on Application-specific Systems, Architectures …, 2007
112007
Post-quantum cryptoprocessors optimized for edge and resource-constrained devices in IoT
S Ebrahimi, S Bayat-Sarmadi, H Mosanaei-Boorani
IEEE Internet of Things Journal 6 (3), 5500-5507, 2019
92019
Fast prototyping with co-operation of simulation and emulation
SB Sarmadi, SG Miremadi, G Asadi, AR Ejlali
International Conference on Field Programmable Logic and Applications, 15-25, 2002
82002
High-Throughput Low-Complexity Unified Multipliers Over in Dual and Triangular Bases
R Salarifard, S Bayat-Sarmadi, M Farmani
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (11), 1944-1953, 2016
52016
Random data and key generation evaluation of some commercial tokens and smart cards
A Boorghany, SB Sarmadi, P Yousefi, P Gorji, R Jalili
2014 11th International ISC Conference on Information Security and …, 2014
52014
Speedup analysis in simulation-emulation co-operation
SG Miremadi, SB Sarmadi, G Asadi
2002 IEEE International Conference on Field-Programmable Technology, 2002 …, 2002
52002
Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over
T Shahroodi, S Bayat-Sarmadi, H Mosanaei-Boorani
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (4), 1465-1473, 2018
42018
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