Norman P. Jouppi
Norman P. Jouppi
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McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures
S Li, JH Ahn, RD Strong, JB Brockman, DM Tullsen, NP Jouppi
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
24712009
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
NP Jouppi
ACM SIGARCH Computer Architecture News 18 (2SI), 364-373, 1990
19851990
In-datacenter performance analysis of a tensor processing unit
NP Jouppi, C Young, N Patil, D Patterson, G Agrawal, R Bajwa, S Bates, ...
Proceedings of the 44th Annual International Symposium on Computer …, 2017
18532017
Complexity-effective superscalar processors
S Palacharla, NP Jouppi, JE Smith
Proceedings of the 24th annual international symposium on Computer …, 1997
12091997
Cacti 3.0: An integrated cache timing, power, and area model
P Shivakumar, NP Jouppi
Technical Report 2001/2, Compaq Computer Corporation, 2001
9962001
Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction
R Kumar, KI Farkas, NP Jouppi, P Ranganathan, DM Tullsen
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
9732003
CACTI: An enhanced cache access and cycle time model
SJE Wilton, NP Jouppi
IEEE Journal of Solid-State Circuits 31 (5), 677-688, 1996
9231996
Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory
X Dong, C Xu, Y Xie, NP Jouppi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
8642012
Corona: System implications of emerging nanophotonic technology
D Vantrease, R Schreiber, M Monchiero, M McLaren, NP Jouppi, ...
ACM SIGARCH Computer Architecture News 36 (3), 153-164, 2008
7752008
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
R Kumar, DM Tullsen, P Ranganathan, NP Jouppi, KI Farkas
Proceedings. 31st Annual International Symposium on Computer Architecture …, 2004
7672004
CACTI 6.0: A tool to model large caches
N Muralimanohar, R Balasubramonian, NP Jouppi
HP laboratories 27, 28, 2009
7472009
CACTI 5.1
S Thoziyoor, N Muralimanohar, JH Ahn, NP Jouppi
Technical Report HPL-2008-20, HP Labs, 2008
7142008
Available instruction-level parallelism for superscalar and superpipelined machines
NP Jouppi, DW Wall
ACM SIGARCH Computer Architecture News 17 (2), 272-282, 1989
5031989
An enhanced access and cycle time model for on-chip caches
SJE Wilton, NP Jouppi
4571993
Heterogeneous chip multiprocessors
R Kumar, DM Tullsen, NP Jouppi, P Ranganathan
Computer 38 (11), 32-38, 2005
4542005
Dynamically selecting processor cores for overall power efficiency
K Farkas, NP Jouppi, RN Mayo, P Ranganathan
US Patent 7,093,147, 2006
4052006
CACTI 4.0
D Tarjan, S Thoziyoor, NP Jouppi
Technical Report HPL-2006-86, HP Laboratories Palo Alto, 2006
3652006
Reconfigurable caches and their application to media processing
P Ranganathan, S Adve, NP Jouppi
ACM SIGARCH Computer Architecture News 28 (2), 214-224, 2000
3572000
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
MS Hrishikesh, NP Jouppi, KI Farkas, D Burger, SW Keckler, ...
Proceedings 29th Annual International Symposium on Computer Architecture, 14-24, 2002
3342002
The multicluster architecture: Reducing cycle time through partitioning
KI Farkas, P Chow, NP Jouppi, Z Vranesic
Proceedings of 30th Annual International Symposium on Microarchitecture, 149-159, 1997
3261997
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Articles 1–20