| Conservation cores: reducing the energy of mature computations G Venkatesh, J Sampson, N Goulding, S Garcia, V Bryksin, ... ACM SIGARCH Computer Architecture News 38 (1), 205-218, 2010 | 567 | 2010 |
| Mixed precision training P Micikevicius, S Narang, J Alben, G Diamos, E Elsen, D Garcia, ... arXiv preprint arXiv:1710.03740, 2017 | 406 | 2017 |
| The GreenDroid mobile application processor: An architecture for silicon's dark future N Goulding-Hotta, J Sampson, G Venkatesh, S Garcia, J Auricchio, ... IEEE Micro 31 (2), 86-95, 2011 | 185 | 2011 |
| QsCores: Trading dark silicon for scalable energy efficiency with quasi-specific cores G Venkatesh, J Sampson, N Goulding-Hotta, SK Venkata, MB Taylor, ... Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 142 | 2011 |
| Unbounded page-based transactional memory W Chuang, S Narayanasamy, G Venkatesh, J Sampson, ... ACM SIGPLAN Notices 41 (11), 347-358, 2006 | 123 | 2006 |
| Accelerating Deep Convolutional Network via Low Precision and Sparsity G Venkatesh, E Nurvitadhi, D Marr Arxiv, 2016 | 117* | 2016 |
| Runnemede: An architecture for ubiquitous high-performance computing NP Carter, A Agrawal, S Borkar, R Cledat, H David, D Dunning, J Fryman, ... High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th …, 2013 | 116 | 2013 |
| Efficient complex operators for irregular codes J Sampson, G Venkatesh, N Goulding-Hotta, S Garcia, S Swanson, ... High Performance Computer Architecture (HPCA), 2011 IEEE 17th International …, 2011 | 47 | 2011 |
| GreenDroid: A mobile application processor for a future of dark silicon N Goulding, J Sampson, G Venkatesh, S Garcia, J Auricchio, J Babb, ... Hot Chips 22, 2010 | 44 | 2010 |
| Hardware accelerator for analytics of sparse data E Nurvitadhi, A Mishra, Y Wang, G Venkatesh, D Marr 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 14 | 2016 |
| An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors J Sampson, M Arora, N Goulding-Hotta, G Venkatesh, J Babb, V Bhatt, ... Field Programmable Logic and Applications (FPL), 2011 International …, 2011 | 8 | 2011 |
| Reducing the energy cost of irregular code bases in soft processor systems M Arora, J Sampson, N Goulding-Hotta, J Babb, G Venkatesh, MB Taylor, ... Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual …, 2011 | 6 | 2011 |
| Efficient sparse array handling in a processor G Venkatesh, TC Zhang, DT Marr US Patent App. 14/747,182, 2016 | 5 | 2016 |
| Exploiting a computation reuse cache to reduce energy in network processors B Li, G Venkatesh, B Calder, R Gupta High Performance Embedded Architectures and Compilers, 251-265, 2005 | 5 | 2005 |
| Scaling the Utilization Wall: The Case for Massively Heterogeneous Multiprocessors I Ahn, N Goudling, J Sampson, G Venkatesh, MB Taylor, SJ Swanson Department of Computer Science and Engineering, University of California …, 2009 | 4 | 2009 |
| APE: accelerator processor extensions to optimize data-compute co-location G Venkatesh Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and …, 2013 | 2 | 2013 |
| Configurable energy-efficient co-processors to scale the utilization wall G Venkatesh | 1 | 2011 |
| Quasi-ASICs: Trading Area for Energy by Exploiting Similarity in Synthesized Cores for Irregular Code G Venkatesh, J Sampson, N Goulding, SJ Swanson, MB Taylor Department of Computer Science and Engineering, University of California …, 2011 | 1 | 2011 |
| Page-Based Transactional Memory to Provide Fast Virtual Transactions W Chuang, S Narayanasamy, G Pokam, J Sampson, M Van Biesbrouck, ... | | |
Jack SampsonAssociate Professor, Pennsylvania State UniversityVerified email at psu.edu
