| A 12 bit 1 GS/s dual-rate hybrid DAC with an 8 GS/s unrolled pipeline delta-sigma modulator achieving> 75 dB SFDR over the Nyquist band S Su, TI Tsai, PK Sharma, MSW Chen IEEE Journal of Solid-State Circuits 50 (4), 896-907, 2015 | 47 | 2015 |
| A 12-bit 2 GS/s dual-rate hybrid DAC with pulse-error pre-distortion and in-band noise cancellation achieving> 74 dBc SFDR and<− 80 dBc IM3 up to 1 GHz in 65 nm CMOS S Su, MSW Chen IEEE Journal of Solid-State Circuits 51 (12), 2963-2978, 2016 | 42 | 2016 |
| Transfer learning with Bayesian optimization-aided sampling for efficient AMS circuit modeling J Liu, M Hassanpourghadi, Q Zhang, S Su, MSW Chen Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 24 | 2020 |
| A 16-bit 12-GS/s single-/dual-rate DAC with a successive bandpass delta-sigma modulator achieving<− 67-dBc IM3 within DC to 6-GHz tunable passbands S Su, MSW Chen IEEE Journal of Solid-State Circuits 53 (12), 3517-3527, 2018 | 23 | 2018 |
| 27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving> 74dBc SFDR up to 1GHz in 65nm CMOS S Su, MSW Chen 2016 IEEE International Solid-State Circuits Conference (ISSCC), 456-457, 2016 | 20 | 2016 |
| 29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving-60dBc Fractional Spur Q Zhang, S Su, CR Ho, MSW Chen 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 410-412, 2021 | 15 | 2021 |
| From specification to silicon: Towards analog/mixed-signal design automation using surrogate NN models with transfer learning J Liu, S Su, M Madhusudan, M Hassanpourghadi, S Saunders, Q Zhang, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 13 | 2021 |
| A Fractional-N Digital MDLL With Background Two-Point DTC Calibration Q Zhang, S Su, CR Ho, MSW Chen IEEE Journal of Solid-State Circuits 57 (1), 80-89, 2021 | 12 | 2021 |
| A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving<-67dBc IM3 within DC-to-6GHz tunable passbands S Su, MSW Chen 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 362-364, 2018 | 12 | 2018 |
| A time-approximation filter for direct RF transmitter S Su, MSW Chen IEEE Journal of Solid-State Circuits 56 (7), 2018-2028, 2020 | 10 | 2020 |
| Circuit connectivity inspired neural network for analog mixed-signal functional modeling M Hassanpourghadi, S Su, RA Rasul, J Liu, Q Zhang, MSW Chen 2021 58th ACM/IEEE Design Automation Conference (DAC), 505-510, 2021 | 9 | 2021 |
| 10.2 A SAW-less direct-digital RF modulator with tri-level time-approximation filter and reconfigurable dual-band delta-sigma modulation S Su, MSW Chen 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 174-176, 2020 | 9 | 2020 |
| CEPA: CNN-based early performance assertion scheme for analog and mixed-signal circuit simulation Q Zhang, S Su, J Liu, MSW Chen Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 8 | 2020 |
| A 1–5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving-43dB EVM at 1024 QAM S Su, MSW Chen 2019 Symposium on VLSI Circuits, C20-C21, 2019 | 8 | 2019 |
| A Millimeter-Wave Mixer-First Receiver with Non-Uniform Time-Approximation Filter Achieving Blocker Rejection C Yang, S Su, MSW Chen 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 3-6, 2022 | 4 | 2022 |
| SAW-less direct RF transmitter with multimode noise shaping and tri-level time-approximation filter S Su, MSW Chen IEEE Journal of Solid-State Circuits 57 (3), 906-916, 2021 | 4 | 2021 |
| TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture S Su, Q Zhang, J Liu, M Hassanpourghadi, R Rasul, MSW Chen 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022 | 3 | 2022 |
| A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving> 75dB SFDR over 500MHz in 65nm CMOS S Su, TI Tsai, P Sharma, MSW Chen 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 3 | 2014 |
| Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration Q Zhang, HC Cheng, S Su, MSW Chen IEEE Journal of Solid-State Circuits, 2023 | 2 | 2023 |
| Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms S Su, Q Zhang, M Hassanpourghadi, J Liu, RA Rasul, MSW Chen 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022 | 2 | 2022 |
Qiaochu ZhangUniversity of Virginia, University of Southern CaliforniaVerified email at virginia.edu
