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Suvadeep Banerjee
Suvadeep Banerjee
Systems Research Scientist, Strategic CAD Labs, Intel Labs
Verified email at intel.com - Homepage
Title
Cited by
Cited by
Year
Toward functional safety of systolic array-based deep learning hardware accelerators
S Kundu, S Banerjee, A Raha, S Natarajan, K Basu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (3), 485-498, 2021
442021
Feedback linearizing indirect adaptive fuzzy control with foraging based on-line plant model estimation
S Banerjee, A Chakrabarty, S Maity, A Chatterjee
Applied Soft Computing, 2011
252011
Fuzzy model predictive control of non-linear processes using convolution models and foraging algorithms
A Chakrabarty, S Banerjee, S Maity, A Chatterjee
Measurement 46 (4), 1616-1629, 2013
192013
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states
S Banerjee, A Chatterjee, JA Abraham
2016 IEEE International Test Conference (ITC), 1-10, 2016
152016
Real-time checking of linear control systems using analog checksums
S Banerjee, A Banerjee, A Chatterjee, JA Abraham
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 122-127, 2013
132013
Real-time error detection in nonlinear control systems using machine learning assisted state-space encoding
S Banerjee, B Samynathan, JA Abraham, A Chatterjee
IEEE transactions on dependable and secure computing 18 (2), 576-592, 2019
112019
Error resilient neuromorphic networks using checker neurons
S Pandey, S Banerjee, A Chatterjee
2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018
102018
Real-time dc motor error detection and control compensation using linear checksums
MI Momtaz, S Banerjee, A Chatterjee
2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016
102016
Statistical video tracking of pomegranate fruits
A Roy, S Banerjee, D Roy, A Mukhopadhyay
2011 Third National Conference on Computer Vision, Pattern Recognition …, 2011
82011
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration
S Banerjee, S Burns, P Cocchini, A Davare, S Jain, D Kirkpatrick, ...
arXiv preprint arXiv:2111.15024, 2021
72021
On-line diagnosis and compensation for parametric failures in linear state variable circuits and systems using time-domain checksum observers
MI Momtaz, S Banerjee, A Chatterjee
2017 IEEE 35th VLSI Test Symposium (VTS), 1-6, 2017
72017
ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks
S Pandey, S Banerjee, A Chatterjee
2018 IEEE 23rd European Test Symposium (ETS), 1-2, 2018
62018
Real-time self-learning for control law adaptation in nonlinear systems using encoded check states
S Banerjee, A Chatterjee
2017 22nd IEEE European Test Symposium (ETS), 1-6, 2017
62017
Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksums
Á Gómez-Pau, S Banerjee, A Chatterjee
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 25-30, 2014
62014
Design of low cost fault tolerant analog circuits using real-time learned error compensation
S Banerjee, Á Gómez-Pau, A Chatterjee
2014 19th IEEE European Test Symposium (ETS), 1-2, 2014
62014
Cross-layer control adaptation for autonomous system resilience
MI Momtaz, S Banerjee, S Pandey, J Abraham, A Chatterjee
2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018
52018
Concurrent error detection and tolerance in kalman filters using encoded state and statistical covariance checks
S Pandey, S Banerjee, A Chatterjee
2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016
52016
Concurrent error detection in nonlinear digital filters using checksum linearization and residue prediction
S Banerjee, MI Momtaz, A Chatterjee
2015 IEEE 21st International On-Line Testing Symposium (IOLTS), 53-58, 2015
52015
Mixed signal design validation using reinforcement learning guided stimulus generation for behavior discovery
B Muldrey, S Banerjee, A Chatterjee
2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019
42019
Infant mortality tests for analog and mixed-signal circuits
S Banerjee, S Natarajan
2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016
42016
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