Mark Heinrich
Mark Heinrich
Associate Professor of Computer Science, UCF
Verified email at - Homepage
Cited by
Cited by
The stanford flash multiprocessor
J Kuskin, D Ofelt, M Heinrich, J Heinlein, R Simoni, K Gharachorloo, ...
Proceedings of 21 International Symposium on Computer Architecture, 302-313, 1994
The performance impact of flexibility in the Stanford FLASH multiprocessor
M Heinrich, J Kuskin, D Ofelt, J Heinlein, J Baxter, JP Singh, R Simoni, ...
Proceedings of the sixth international conference on Architectural support …, 1994
FLASH vs.(simulated) FLASH: Closing the simulation loop
J Gibson, R Kunz, D Ofelt, M Horowitz, J Hennessy, M Heinrich
ACM SIGPLAN Notices 35 (11), 49-58, 2000
The effects of latency, occupancy, and bandwidth in distributed shared memory multiprocessors
C Holt, M Heinrich, JP Singh, E Rothberg, J Hennessy
Technical Report CSL-TR-95-660, Computer Systems Laboratory, Stanford University, 1995
Systems, Devices, and Methods for Transferring Digital Information
A Erlichson, M Heinrich
US Patent App. 11/995,629, 2009
Integrating performance monitoring and communication in parallel computers
M Martonosi, D Ofelt, M Heinrich
ACM SIGMETRICS Performance Evaluation Review 24 (1), 138-147, 1996
Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors
V Soundararajan, M Heinrich, B Verghese, K Gharachorloo, A Gupta, ...
Proceedings. 25th Annual International Symposium on Computer Architecture …, 1998
Cache-coherent distributed shared memory: Perspectives on its development and future challenges
J Hennessy, M Heinrich, A Gupta
Proceedings of the IEEE 87 (3), 418-429, 1999
Digital system simulation: Methodologies and examples
K Olukotun, M Heinrich, D Ofelt
Proceedings 1998 Design and Automation Conference. 35th DAC.(Cat. No …, 1998
A quantitative analysis of the performance and scalability of distributed shared memory cache coherence protocols
M Heinrich, V Soundararajan, J Hennessy, A Gupta
IEEE Transactions on Computers 48 (2), 205-217, 1999
Leveraging cache coherence in active memory systems
D Kim, M Chaudhuri, M Heinrich
Proceedings of the 16th international conference on Supercomputing, 2-13, 2002
The Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols
MA Heinrich
Stanford University, 1998
Using meta-level compilation to check FLASH protocol code
A Chou, B Chelf, D Engler, M Heinrich
ACM SIGARCH Computer Architecture News 28 (5), 59-70, 2000
SMTp: an architecture for next-generation scalable multi-threading
M Chaudhuri, M Heinrich
ACM SIGARCH Computer Architecture News 32 (2), 124, 2004
Cache Coherence Protocol Design for Active Memory Systems.
M Chaudhuri, D Kim, MA Heinrich
PDPTA, 83-89, 2002
Latency, occupancy, and bandwidth in DSM multiprocessors: a performance evaluation
M Chaudhuri, M Heinrich, C Holt, JP Singh, E Rothberg, J Hennessy
IEEE Transactions on Computers 52 (7), 862-880, 2003
The stanford flash multiprocessor
J Kuskin, D Ofelt, M Heinrich, J Heinlein, R Simoni, K Gharachorloo, ...
25 years of the international symposia on Computer architecture (selected …, 1998
Architectural support for uniprocessor and multiprocessor active memory systems
D Kim, M Chaudhuri, M Heinrich, E Speight
IEEE Transactions on Computers 53 (3), 288-307, 2004
Hardware/software co-design of the stanford FLASH multiprocessor
M Heinrich, D Ofelt, MA Horowitz, J Hennessy
Proceedings of the IEEE 85 (3), 455-466, 1997
The impact of negative acknowledgments in shared memory scientific applications
M Chaudhuri, M Heinrich
IEEE Transactions on Parallel and Distributed Systems 15 (2), 134-150, 2004
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