Very compact FPGA implementation of the AES algorithm P Chodowiec, K Gaj International Workshop on Cryptographic Hardware and Embedded Systems, 319-333, 2003 | 400 | 2003 |

Comparison of the hardware performance of the AES candidates using reconfigurable hardware K Gaj, P Chodowiec | 224 | 2001 |

The promise of high-performance reconfigurable computing T El-Ghazawi, E El-Araby, M Huang, K Gaj, V Kindratenko, D Buell Computer 41 (2), 69-76, 2008 | 210 | 2008 |

An embedded true random number generator for FPGAs P Kohlbrenner, K Gaj Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004 | 186 | 2004 |

Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays K Gaj, P Chodowiec Cryptographers’ Track at the RSA Conference, 84-99, 2001 | 178 | 2001 |

Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs K Gaj, E Homsirikamol, M Rogawski International Workshop on Cryptographic Hardware and Embedded Systems, 264-278, 2010 | 136 | 2010 |

Fast implementations of secret-key block ciphers using mixed inner-and outer-round pipelining P Chodowiec, P Khuon, K Gaj Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field …, 2001 | 126 | 2001 |

Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512 T Grembowski, R Lien, K Gaj, N Nguyen, P Bellows, J Flidr, T Lehman, ... International Conference on Information Security, 75-89, 2002 | 122 | 2002 |

FPGA and ASIC implementations of AES K Gaj, P Chodowiec Cryptographic engineering, 235-294, 2009 | 121 | 2009 |

New hardware architectures for Montgomery modular multiplication algorithm M Huang, K Gaj, T El-Ghazawi IEEE Transactions on computers 60 (7), 923-936, 2010 | 100 | 2010 |

Guest editors' introduction: High-performance reconfigurable computing D Buell, T El-Ghazawi, K Gaj, V Kindratenko Computer 40 (3), 23-27, 2007 | 100 | 2007 |

Timing of multi-gigahertz rapid single flux quantum digital circuits K Gaj, EG Friedman, MJ Feldman Journal of VLSI signal processing systems for signal, image and video …, 1997 | 95 | 1997 |

ATHENa-automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs K Gaj, JP Kaps, V Amirineni, M Rogawski, E Homsirikamol, BY Brewster 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 91 | 2010 |

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs. K Gaj, E Homsirikamol, M Rogawski, R Shahid, MU Sharif IACR Cryptol. ePrint Arch. 2012, 368, 2012 | 82 | 2012 |

A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512 R Lien, T Grembowski, K Gaj Cryptographers’ Track at the RSA Conference, 324-338, 2004 | 78 | 2004 |

Experimental testing of the gigabit IPSec-Compliant implementations of Rijndael and triple DES using SLAAC-1V FPGA accelerator board P Chodowiec, K Gaj, P Bellows, B Schott International Conference on Information Security, 220-234, 2001 | 75 | 2001 |

Tools for the computer-aided design of multigigahertz superconducting digital circuits K Gaj, QP Herr, V Adler, A Krasniewski, EG Friedman, MJ Feldman IEEE transactions on applied superconductivity 9 (1), 18-38, 1999 | 66 | 1999 |

FPGA accelerated Tate pairing based cryptosystems over binary fields C Shu, S Kwon, K Gaj 2006 IEEE International Conference on Field Programmable Technology, 173-180, 2006 | 62 | 2006 |

A configurable ring-oscillator-based PUF for Xilinx FPGAs X Xin, JP Kaps, K Gaj 2011 14th Euromicro Conference on Digital System Design, 651-657, 2011 | 61 | 2011 |

Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates D Hwang, M Chaney, S Karanam, N Ton, K Gaj The State of the Art of Stream Ciphers, 151-162, 2008 | 60 | 2008 |