| Low-current perpendicular domain wall motion cell for scalable high-speed MRAM S Fukami, T Suzuki, K Nagahara, N Ohshima, Y Ozaki, S Saito, R Nebashi, ... 2009 Symposium on VLSI Technology, 230-231, 2009 | 208 | 2009 |
| A 90nm 12ns 32Mb 2T1MTJ MRAM R Nebashi, N Sakimura, H Honjo, S Saito, Y Ito, S Miura, Y Kato, K Mori, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 144 | 2009 |
| 10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications N Sakimura, Y Tsuji, R Nebashi, H Honjo, A Morioka, K Ishihara, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 106 | 2014 |
| A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture S Matsunaga, S Miura, H Honjou, K Kinoshita, S Ikeda, T Endoh, H Ohno, ... 2012 Symposium on VLSI Circuits (VLSIC), 44-45, 2012 | 104 | 2012 |
| MRAM cell technology for over 500-MHz SoC N Sakimura, T Sugibayashi, T Honda, H Honjo, S Saito, T Suzuki, ... IEEE journal of solid-state circuits 42 (4), 830-838, 2007 | 102 | 2007 |
| A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme T Ohsawa, H Koike, S Miura, H Honjo, K Kinoshita, S Ikeda, T Hanyu, ... IEEE Journal of Solid-State Circuits 48 (6), 1511-1520, 2013 | 88 | 2013 |
| Determination of the proton tunneling splitting of tropolone in the ground state by microwave spectroscopy K Tanaka, H Honjo, T Tanaka, H Kohguchi, Y Ohshima, Y Endo The Journal of chemical physics 110 (4), 1969-1978, 1999 | 87 | 1999 |
| Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... IEEE Journal of Solid-State Circuits 50 (2), 476-489, 2014 | 72 | 2014 |
| A recent progress of spintronics devices for integrated circuit applications T Endoh, H Honjo Journal of Low Power Electronics and Applications 8 (4), 44, 2018 | 70 | 2018 |
| Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 70 | 2013 |
| 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0 ns/200ps wake-up/power-off times T Ohsawa, H Koike, S Miura, H Honjo, K Tokutome, S Ikeda, T Hanyu, ... 2012 symposium on VLSI circuits (VLSIC), 46-47, 2012 | 66 | 2012 |
| Magnetoresistive effect transducer having longitudinal bias layer directly connected to free layer K Hayashi, K Ohashi, N Ishiwata, M Nakada, T Ishi, H Honjou, K Ishihara, ... US Patent 6,950,290, 2005 | 60 | 2005 |
| First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400° C thermal tolerance by canted SOT structure and its advanced patterning … H Honjo, TVA Nguyen, T Watanabe, T Nasuno, C Zhang, T Tanigawa, ... 2019 IEEE International Electron Devices Meeting (IEDM), 28.5. 1-28.5. 4, 2019 | 58 | 2019 |
| Co/Pt multilayer based reference layers in magnetic tunnel junctions for nonvolatile spintronics VLSIs H Sato, S Ikeda, S Fukami, H Honjo, S Ishikawa, M Yamanouchi, ... Japanese Journal of Applied Physics 53 (4S), 04EM02, 2014 | 54 | 2014 |
| Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure D Suzuki, M Natsui, A Mochizuki, S Miura, H Honjo, H Sato, S Fukami, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C172-C173, 2015 | 53 | 2015 |
| High-speed simulator including accurate MTJ models for spintronics integrated circuit design N Sakimura, R Nebashi, Y Tsuji, H Honjo, T Sugibayashi, H Koike, ... 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 1971-1974, 2012 | 52 | 2012 |
| A 47.14- 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications M Natsui, D Suzuki, A Tamakoshi, T Watanabe, H Honjo, H Koike, ... IEEE Journal of Solid-State Circuits 54 (11), 2991-3004, 2019 | 51 | 2019 |
| 14ns write speed 128Mb density Embedded STT-MRAM with endurance>1010 and 10yrs retention@85°C using novel low damage MTJ integration process H Sato, H Honjo, T Watanabe, M Niwa, H Koike, S Miura, T Saito, H Inoue, ... 2018 IEEE International Electron Devices Meeting (IEDM), 27.2. 1-27.2. 4, 2018 | 50 | 2018 |
| Perpendicular-anisotropy CoFeB-MgO based magnetic tunnel junctions scaling down to 1X nm S Ikeda, H Sato, H Honjo, ECI Enobio, S Ishikawa, M Yamanouchi, ... 2014 IEEE International Electron Devices Meeting, 33.2. 1-33.2. 4, 2014 | 48 | 2014 |
| A 1.5 nsec/2.1 nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories T Ohsawa, S Miura, K Kinoshita, H Honjo, S Ikeda, T Hanyu, H Ohno, ... 2013 Symposium on VLSI Circuits, C110-C111, 2013 | 48 | 2013 |
Shoji IkedaTohoku UniversityVerified email at cies.tohoku.ac.jp
