Michael Chu
Michael Chu
Senior Member of Technical Staff, AMD Research
Verified email at umich.edu
Cited by
Cited by
Hybrid transactional memory
S Kumar, M Chu, CJ Hughes, P Kundu, A Nguyen
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006
An architecture framework for transparent instruction set customization in embedded processors
N Clark, J Blome, M Chu, S Mahlke, S Biles, K Flautner
32nd International Symposium on Computer Architecture (ISCA'05), 272-283, 2005
Region-based hierarchical operation partitioning for multicluster processors
M Chu, K Fan, S Mahlke
Proceedings of the ACM SIGPLAN 2003 conference on Programming language …, 2003
Data access partitioning for fine-grain parallelism on multicore architectures
M Chu, R Ravindran, S Mahlke
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
Aurantimonas manganoxydans, sp. nov. and Aurantimonas litoralis, sp. nov.: Mn(II) Oxidizing Representatives of a Globally Distributed Clade of alpha-Proteobacteria from …
CR Anderson, GJ Dick, ML Chu, JC Cho, RE Davis, SL Bräuer, BM Tebo
Geomicrobiology Journal 26 (3), 189-198, 2009
Systematic register bypass customization for application-specific processors
K Fan, N Clark, M Chu, KV Manjunath, R Ravindran, M Smelyanskiy, ...
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
Compiler-managed partitioned data caches for low power
R Ravindran, M Chu, S Mahlke
ACM SIGPLAN Notices 42 (7), 237-247, 2007
Compiler-directed data partitioning for muiticluster processors
ML Chu, SA Mahlke
International Symposium on Code Generation and Optimization (CGO'06), 11 pp.-220, 2006
Runtime agnostic representation of user code for execution with selected execution runtime
K Varadarajan, ML Chu
US Patent 9,658,890, 2017
FLASH: Foresighted latency-aware scheduling heuristic for processors with customized datapaths
M Kudlur, K Fan, M Chu, R Ravindran, N Clark, S Mahlke
International Symposium on Code Generation and Optimization, 2004. CGO 2004 …, 2004
Dynamic data and compute resource elasticity
K Varadarajan, ML Chu
US Patent 9,600,255, 2017
Verification of a dataflow representation of a program through static type-checking
K Varadarajan, ML Chu
US Patent 9,760,348, 2017
Declarative programming model with a native programming language
K Varadarajan, ML Chu
US Patent 9,600,250, 2017
Extended task queuing: Active messages for heterogeneous systems
M LeBeane, B Potter, A Pan, A Dutu, V Agarwala, W Lee, D Majeti, ...
SC'16: Proceedings of the International Conference for High Performance …, 2016
Automatic synthesis of customized local memories for multicluster application accelerators
M Kudlur, K Fan, M Chu, S Mahlke
Proceedings. 15th IEEE International Conference on Application-Specific …, 2004
Taming irregular applications via advanced dynamic parallelism on GPUs
J Zhang, AM Aji, ML Chu, H Wang, W Feng
Proceedings of the 15th ACM International Conference on Computing Frontiers …, 2018
Cost-Sensitive Operation Partitioning for Synthesizing Custom Multicluster Datapath Architectures
ML Chu, KC Fan, RA Ravindran, SA Mahlke
Proc. 2nd Workshop on Application Specific Processors, 40-47, 2003
Remote task queuing by networked computing devices
SK Reinhardt, ML Chu, V Tipparaju, WB Benton
US Patent 9,582,402, 2017
Dynamic data and compute resource elasticity
K Varadarajan, ML Chu
US Patent 10,592,218, 2020
Adaptive Task Aggregation for High-Performance Sparse Solvers on GPUs
AE Helal, AM Aji, ML Chu, BM Beckmann, W Feng
2019 28th International Conference on Parallel Architectures and Compilation …, 2019
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