Cong Xu
Cong Xu
Research Scientist, Hewlett Packard Labs
Verified email at
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Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory
P Chi, S Li, C Xu, T Zhang, J Zhao, Y Liu, Y Wang, Y Xie
ACM SIGARCH Computer Architecture News 44 (3), 27-39, 2016
Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory
X Dong, C Xu, Y Xie, NP Jouppi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
Terngrad: Ternary gradients to reduce communication in distributed deep learning
W Wen, C Xu, F Yan, C Wu, Y Wang, Y Chen, H Li
Advances in neural information processing systems 30, 2017
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories
S Li, C Xu, Q Zou, J Zhao, Y Lu, Y Xie
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
Overcoming the challenges of crossbar resistive memory architectures
C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie
2015 IEEE 21st international symposium on high performance computer …, 2015
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
A Jog, AK Mishra, C Xu, Y Xie, V Narayanan, R Iyer, CR Das
DAC Design Automation Conference 2012, 243-252, 2012
Design implications of memristor-based RRAM cross-point structures
C Xu, X Dong, NP Jouppi, Y Xie
2011 Design, Automation & Test in Europe, 1-6, 2011
Impact of process variations on emerging memristor
D Niu, Y Chen, C Xu, Y Xie
Proceedings of the 47th Design Automation Conference, 877-882, 2010
Coordinating filters for faster deep neural networks
W Wen, C Xu, C Wu, Y Wang, Y Chen, H Li
Proceedings of the IEEE International Conference on Computer Vision, 658-666, 2017
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
Z Wang, DA Jiménez, C Xu, G Sun, Y Xie
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
Understanding the trade-offs in multi-level cell ReRAM memory design
C Xu, D Niu, N Muralimanohar, NP Jouppi, Y Xie
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2013
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation
T Zhang, K Chen, C Xu, G Sun, T Wang, Y Xie
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
Design trade-offs for high density cross-point resistive memory
D Niu, C Xu, N Muralimanohar, NP Jouppi, Y Xie
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost
D Niu, C Xu, N Muralimanohar, NP Jouppi, Y Xie
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 17-23, 2013
CREAM: A concurrent-refresh-aware DRAM memory architecture
T Zhang, M Poremba, C Xu, G Sun, Y Xie
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
C Xu, D Niu, X Zhu, SH Kang, M Nowak, Y Xie
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 463-470, 2011
Low power multi-level-cell resistive memory design with incomplete data mapping
D Niu, Q Zou, C Xu, Y Xie
2013 IEEE 31st International Conference on Computer Design (ICCD), 131-137, 2013
Moguls: a model to explore the memory hierarchy for bandwidth improvements
G Sun, CJ Hughes, C Kim, J Zhao, C Xu, Y Xie, YK Chen
Acm Sigarch Computer Architecture News 39 (3), 377-388, 2011
Modeling and design analysis of 3D vertical resistive memory—A low cost cross-point architecture
C Xu, D Niu, S Yu, Y Xie
2014 19th Asia and South Pacific design automation conference (ASP-DAC), 825-830, 2014
Memory that never forgets: emerging nonvolatile memory and the implication for architecture design
G Sun, J Zhao, M Poremba, C Xu, Y Xie
National Science Review 5 (4), 577-592, 2018
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